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| author | Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> | 2014-05-08 08:53:09 +0300 |
|---|---|---|
| committer | Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> | 2014-05-08 09:02:50 +0300 |
| commit | 999b995ddc4a8a2f146ebf9a46c9924c6a7c65a6 (patch) | |
| tree | 668d90849443ac904a35a71a867e08a0484a8de9 /sim | |
| parent | efefdd63628d540f3ad513b2bb2036dfc53f00a8 (diff) | |
| download | gdb-999b995ddc4a8a2f146ebf9a46c9924c6a7c65a6.zip gdb-999b995ddc4a8a2f146ebf9a46c9924c6a7c65a6.tar.gz gdb-999b995ddc4a8a2f146ebf9a46c9924c6a7c65a6.tar.bz2 | |
or1k: add support for l.swa/l.lwa atomic instructions
This adds support for the load-link/store-conditional
l.lwa/l.swa atomic instructions.
The support is added in such way, that the cpu description not
only describes the mnemonics, but also the functionality.
A couple of fixes to typos in nearby/related code are also snuck
into this.
cpu/
* or1korbis.cpu (h-atomic-reserve): New hardware.
(h-atomic-address): Likewise.
(insn-opcode): Add opcodes for LWA and SWA.
(atomic-reserve): New operand.
(atomic-address): Likewise.
(l-lwa, l-swa): New instructions.
(l-lbs): Fix typo in comment.
(store-insn): Clear atomic reserve on store to atomic-address.
Fix register names in fmt field.
opcodes/
* or1k-desc.c: Regenerated.
* or1k-desc.h: Likewise.
* or1k-opc.c: Likewise.
* or1k-opc.h: Likewise.
* or1k-opinst.c: Likewise.
Diffstat (limited to 'sim')
0 files changed, 0 insertions, 0 deletions