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| author | Frank Ch. Eigler <fche@redhat.com> | 2000-06-20 21:12:33 +0000 |
|---|---|---|
| committer | Frank Ch. Eigler <fche@redhat.com> | 2000-06-20 21:12:33 +0000 |
| commit | 97ee9e5aa98ce33445a4951fb57af7925884b156 (patch) | |
| tree | 65736b9b62606b453295a0e087fe5bf3cd7f7840 /sim | |
| parent | bbeb2e037c923b5834cac420e7567ecd725bd18d (diff) | |
| download | gdb-97ee9e5aa98ce33445a4951fb57af7925884b156.zip gdb-97ee9e5aa98ce33445a4951fb57af7925884b156.tar.gz gdb-97ee9e5aa98ce33445a4951fb57af7925884b156.tar.bz2 | |
* build fix
2000-06-20 Frank Ch. Eigler <fche@redhat.com>
* compile.c: Don't include "wait.h".
(sim_resume): Use local SIM_WIFEXITED and SIM_WIFSIGNALED macros
instead of WIF* from host.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/h8300/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/h8300/compile.c | 26 |
2 files changed, 11 insertions, 21 deletions
diff --git a/sim/h8300/ChangeLog b/sim/h8300/ChangeLog index 4721e89..e3885de 100644 --- a/sim/h8300/ChangeLog +++ b/sim/h8300/ChangeLog @@ -1,3 +1,9 @@ +2000-06-20 Frank Ch. Eigler <fche@redhat.com> + + * compile.c: Don't include "wait.h". + (sim_resume): Use local SIM_WIFEXITED and SIM_WIFSIGNALED macros + instead of WIF* from host. + 2000-06-13 Frank Ch. Eigler <fche@redhat.com> * compile.c, writecode.c: Correct typo. diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c index 81aca5e..bbd28e5 100644 --- a/sim/h8300/compile.c +++ b/sim/h8300/compile.c @@ -30,7 +30,6 @@ #ifdef HAVE_SYS_PARAM_H #include <sys/param.h> #endif -#include "wait.h" #include "ansidecl.h" #include "bfd.h" #include "callback.h" @@ -1355,32 +1354,17 @@ sim_resume (sd, step, siggnal) cpu.exception = SIGILL; goto end; case O (O_SLEEP, SN): - /* The format of r0 is defined by devo/include/wait.h. */ -#if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */ - if (WIFEXITED (cpu.regs[0])) - { - cpu.state = SIM_STATE_EXITED; - cpu.exception = WEXITSTATUS (cpu.regs[0]); - } - else if (WIFSTOPPED (cpu.regs[0])) - { - cpu.state = SIM_STATE_STOPPED; - cpu.exception = WSTOPSIG (cpu.regs[0]); - } - else - { - cpu.state = SIM_STATE_SIGNALLED; - cpu.exception = WTERMSIG (cpu.regs[0]); - } -#else /* FIXME: Doesn't this break for breakpoints when r0 contains just the right (er, wrong) value? */ cpu.state = SIM_STATE_STOPPED; - if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0])) + /* The format of r0 is defined by target newlib. Expand + the macros here instead of looking for .../sys/wait.h. */ +#define SIM_WIFEXITED(v) (((v) & 0xff) == 0) +#define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f)) + if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0])) cpu.exception = SIGILL; else cpu.exception = SIGTRAP; -#endif goto end; case O (O_BPT, SN): cpu.state = SIM_STATE_STOPPED; |