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authorAndrew Cagney <cagney@redhat.com>1997-11-11 12:31:24 +0000
committerAndrew Cagney <cagney@redhat.com>1997-11-11 12:31:24 +0000
commita94c5493a74f965bb0fac3e0c6caf0621cb3097f (patch)
treec9c5add8ecdbf76c0dba5866f83ba0cdd4302377 /sim
parent030843d7f82aaf1ea2752cbdbb79013256acb847 (diff)
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Make the signess of compares between GPR's explicit using a cast to
signed_word.
Diffstat (limited to 'sim')
-rw-r--r--sim/mips/ChangeLog5
-rw-r--r--sim/mips/mips.igen95
2 files changed, 39 insertions, 61 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 53a3d30..8f685b8 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -6,11 +6,12 @@ Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
(LWXC1, SWXC1): Delete from r5900 instruction set.
(end-sanitize-r5900):
(MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
- PENDING_FILL versions of instructions.
+ PENDING_FILL versions of instructions. Simplify.
(X): New function.
(MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
instructions.
- (BEQZ, ...): Explicitly cast GPR to a signed value.
+ (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
+ a signed value.
(MTHI, MFHI): Disable code checking HI-LO.
* sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 2b7785b..955ec68 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -2706,7 +2706,7 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RD] = (GPR[RS] < GPR[RT]);
+ GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
}
@@ -2727,7 +2727,7 @@
*tx19:
// end-sanitize-tx19
{
- GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE));
+ GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
}
@@ -3158,7 +3158,7 @@
*tx19:
// end-sanitize-tx19
{
- if (GPR[RS] == GPR[RT])
+ if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
}
@@ -3179,7 +3179,7 @@
*tx19:
// end-sanitize-tx19
{
- if (GPR[RS] == EXTEND16 (IMMEDIATE))
+ if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
}
@@ -3200,7 +3200,7 @@
*tx19:
// end-sanitize-tx19
{
- if (GPR[RS] >= GPR[RT])
+ if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
}
@@ -3221,7 +3221,7 @@
*tx19:
// end-sanitize-tx19
{
- if (GPR[RS] >= EXTEND16 (IMMEDIATE))
+ if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
}
@@ -3284,7 +3284,7 @@
*tx19:
// end-sanitize-tx19
{
- if (GPR[RS] < GPR[RT])
+ if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
}
@@ -3305,7 +3305,7 @@
*tx19:
// end-sanitize-tx19
{
- if (GPR[RS] < EXTEND16 (IMMEDIATE))
+ if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
}
@@ -3368,7 +3368,7 @@
*tx19:
// end-sanitize-tx19
{
- if (GPR[RS] != GPR[RT])
+ if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
}
@@ -3389,7 +3389,7 @@
*tx19:
// end-sanitize-tx19
{
- if (GPR[RS] != EXTEND16 (IMMEDIATE))
+ if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
}
@@ -4074,7 +4074,7 @@
110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
-"ldc1 f<FD>, <OFFSET>(r<BASE>)"
+"ldc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsII:
*mipsIII:
*mipsIV:
@@ -4086,31 +4086,18 @@
*tx19:
// end-sanitize-tx19
{
- signed_word offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16);
- int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
- signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((uword64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- uword64 memval = 0;
- uword64 memval1 = 0;
- uword64 mask = 0x7;
- unsigned int shift = 4;
- unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte UNUSED;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
- }
- }
- }
+ address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
+ address_word paddr;
+ int uncached;
+ if ((vaddr & 7) != 0)
+ SignalExceptionAddressLoad();
+ else
+ {
+ unsigned64 memval;
+ AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
+ LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
+ COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
+ }
}
@@ -4747,32 +4734,22 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16);
- int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
- signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((uword64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- uword64 memval = 0;
- uword64 memval1 = 0;
- memval = (uword64)COP_SD(((instruction >> 26) & 0x3),destreg);
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
+ int uncached;
+ if ((vaddr & 7) != 0)
+ SignalExceptionAddressStore();
+ else
+ {
+ address_word paddr;
+ unsigned64 memval;
+ AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
+ memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
+ StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
+ }
}
+
010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
*mipsIV:
// start-sanitize-vr5400