diff options
| author | nobody <> | 2004-03-23 23:05:53 +0000 |
|---|---|---|
| committer | nobody <> | 2004-03-23 23:05:53 +0000 |
| commit | 58d880d7dc46ef22215df77fa468d76cad99a900 (patch) | |
| tree | fce9429309a4e5745ddd79402c973d2915569175 /sim | |
| parent | 51550d1a9e579cc2163fc6f09744867302f12fb5 (diff) | |
| download | gdb-58d880d7dc46ef22215df77fa468d76cad99a900.zip gdb-58d880d7dc46ef22215df77fa468d76cad99a900.tar.gz gdb-58d880d7dc46ef22215df77fa468d76cad99a900.tar.bz2 | |
This commit was manufactured by cvs2svn to create branchezannoni_pie-20040323-branchpoint
'ezannoni_pie-20040323-branch'.
Sprout from gdb_6_1-branch 2004-03-12 17:46:28 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_6_1-branch'.'
Cherrypick from gdb_6_1-branch 2004-03-09 17:34:40 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_6_1-branch'.':
gdb/testsuite/gdb.cp/classes.cc
Cherrypick from master 2004-03-23 23:05:52 UTC Paul Brook <paul@codesourcery.com> ' * bfd/elf32-arm.h (arm_print_private_bfd_data): Add EABI v3.':
ChangeLog
Makefile.in
Makefile.tpl
bfd/ChangeLog
bfd/Makefile.am
bfd/Makefile.in
bfd/aclocal.m4
bfd/aix386-core.c
bfd/archive.c
bfd/archures.c
bfd/bfd-in.h
bfd/bfd-in2.h
bfd/coff-tic54x.c
bfd/config.bfd
bfd/config.in
bfd/configure
bfd/configure.in
bfd/cpu-frv.c
bfd/cpu-sh.c
bfd/doc/ChangeLog
bfd/doc/Makefile.in
bfd/dwarf2.c
bfd/elf-bfd.h
bfd/elf-hppa.h
bfd/elf-m10200.c
bfd/elf-m10300.c
bfd/elf.c
bfd/elf32-arm.h
bfd/elf32-avr.c
bfd/elf32-cris.c
bfd/elf32-d10v.c
bfd/elf32-fr30.c
bfd/elf32-frv.c
bfd/elf32-h8300.c
bfd/elf32-hppa.c
bfd/elf32-i370.c
bfd/elf32-i386.c
bfd/elf32-i860.c
bfd/elf32-ip2k.c
bfd/elf32-iq2000.c
bfd/elf32-m32r.c
bfd/elf32-m68hc1x.c
bfd/elf32-m68k.c
bfd/elf32-mcore.c
bfd/elf32-msp430.c
bfd/elf32-openrisc.c
bfd/elf32-ppc.c
bfd/elf32-s390.c
bfd/elf32-sh.c
bfd/elf32-sparc.c
bfd/elf32-v850.c
bfd/elf32-vax.c
bfd/elf32-xstormy16.c
bfd/elf32-xtensa.c
bfd/elf64-alpha.c
bfd/elf64-hppa.c
bfd/elf64-mmix.c
bfd/elf64-ppc.c
bfd/elf64-s390.c
bfd/elf64-sh64.c
bfd/elf64-sparc.c
bfd/elf64-x86-64.c
bfd/elflink.c
bfd/elflink.h
bfd/elfxx-ia64.c
bfd/elfxx-mips.c
bfd/hppabsd-core.c
bfd/hpux-core.c
bfd/irix-core.c
bfd/libaout.h
bfd/libbfd.c
bfd/linker.c
bfd/mach-o.c
bfd/netbsd-core.c
bfd/osf-core.c
bfd/pdp11.c
bfd/po/bfd.pot
bfd/ptrace-core.c
bfd/sco5-core.c
bfd/targets.c
bfd/trad-core.c
bfd/version.h
config/ChangeLog
config/accross.m4
config/acx.m4
configure
configure.in
cpu/ChangeLog
cpu/frv.cpu
cpu/frv.opc
gdb/ChangeLog
gdb/MAINTAINERS
gdb/Makefile.in
gdb/NEWS
gdb/PROBLEMS
gdb/alpha-linux-tdep.c
gdb/alpha-osf1-tdep.c
gdb/alpha-tdep.c
gdb/alphafbsd-tdep.c
gdb/alphanbsd-tdep.c
gdb/amd64-linux-nat.c
gdb/amd64-linux-tdep.c
gdb/amd64-nat.c
gdb/amd64-tdep.c
gdb/amd64-tdep.h
gdb/amd64bsd-nat.c
gdb/amd64fbsd-nat.c
gdb/amd64nbsd-tdep.c
gdb/amd64obsd-tdep.c
gdb/arch-utils.c
gdb/arch-utils.h
gdb/arm-tdep.c
gdb/bcache.c
gdb/blockframe.c
gdb/breakpoint.c
gdb/config/alpha/fbsd.mt
gdb/config/alpha/nm-fbsd.h
gdb/config/arm/tm-embed.h
gdb/config/arm/tm-linux.h
gdb/config/frv/frv.mt
gdb/config/frv/tm-frv.h
gdb/config/i386/nm-fbsd.h
gdb/config/i386/nm-fbsd64.h
gdb/config/i386/nm-obsd.h
gdb/config/ia64/tm-aix.h
gdb/config/ia64/tm-linux.h
gdb/config/m68k/tm-nbsd.h
gdb/config/mips/tm-irix5.h
gdb/config/mips/tm-irix6.h
gdb/config/mips/tm-linux.h
gdb/config/mips/tm-nbsd.h
gdb/config/nm-bsd.h
gdb/config/pa/tm-hppa.h
gdb/config/pa/tm-hppa64.h
gdb/config/powerpc/tm-linux.h
gdb/config/rs6000/tm-rs6000.h
gdb/config/sparc/nm-fbsd.h
gdb/config/vax/tm-vaxbsd.h
gdb/cp-namespace.c
gdb/cris-tdep.c
gdb/doc/ChangeLog
gdb/doc/gdb.texinfo
gdb/doc/gdbint.texinfo
gdb/dummy-frame.c
gdb/dummy-frame.h
gdb/dwarf2-frame.c
gdb/dwarf2read.c
gdb/frame-base.c
gdb/frame-unwind.c
gdb/frame-unwind.h
gdb/frame.c
gdb/frame.h
gdb/frv-linux-tdep.c
gdb/frv-tdep.c
gdb/frv-tdep.h
gdb/gdb_obstack.h
gdb/gdbarch.c
gdb/gdbarch.h
gdb/gdbarch.sh
gdb/gdbserver/ChangeLog
gdb/gdbserver/Makefile.in
gdb/gdbserver/gdbreplay.c
gdb/gdbserver/linux-low.c
gdb/gdbserver/server.c
gdb/gdbserver/server.h
gdb/gdbserver/target.c
gdb/gdbserver/target.h
gdb/gdbserver/utils.c
gdb/gdbtypes.c
gdb/gnu-v3-abi.c
gdb/h8300-tdep.c
gdb/hppa-hpux-tdep.c
gdb/hppa-tdep.c
gdb/i386-interix-tdep.c
gdb/i386-linux-tdep.c
gdb/i386-nat.c
gdb/i386-nto-tdep.c
gdb/i386-sol2-tdep.c
gdb/i386-tdep.c
gdb/i386-tdep.h
gdb/i386bsd-nat.c
gdb/i386bsd-tdep.c
gdb/i386nbsd-tdep.c
gdb/i386obsd-tdep.c
gdb/i387-tdep.c
gdb/i387-tdep.h
gdb/ia64-tdep.c
gdb/infcall.c
gdb/infcmd.c
gdb/inferior.h
gdb/infrun.c
gdb/libunwind-frame.c
gdb/lin-lwp.c
gdb/m68hc11-tdep.c
gdb/m68k-tdep.c
gdb/m68klinux-tdep.c
gdb/mcore-tdep.c
gdb/mips-linux-tdep.c
gdb/mips-tdep.c
gdb/mipsnbsd-tdep.c
gdb/mn10300-tdep.c
gdb/ppc-linux-nat.c
gdb/ppc-linux-tdep.c
gdb/ppc-tdep.h
gdb/ppcnbsd-tdep.c
gdb/regcache.c
gdb/reggroups.c
gdb/remote-m32r-sdi.c
gdb/remote.c
gdb/rs6000-tdep.c
gdb/s390-tdep.c
gdb/sh-tdep.c
gdb/sh64-tdep.c
gdb/shnbsd-tdep.c
gdb/solib-frv.c
gdb/solib-svr4.c
gdb/solib-svr4.h
gdb/solib.c
gdb/solist.h
gdb/sparc-linux-tdep.c
gdb/sparc-sol2-tdep.c
gdb/sparc-tdep.c
gdb/sparc64-sol2-tdep.c
gdb/sparc64fbsd-tdep.c
gdb/sparc64nbsd-tdep.c
gdb/sparc64obsd-tdep.c
gdb/sparcnbsd-tdep.c
gdb/sparcobsd-tdep.c
gdb/stabsread.c
gdb/stack.c
gdb/symtab.h
gdb/target.c
gdb/testsuite/ChangeLog
gdb/testsuite/gdb.asm/openbsd.inc
gdb/testsuite/gdb.base/auxv.c
gdb/testsuite/gdb.base/auxv.exp
gdb/testsuite/gdb.base/pc-fp.exp
gdb/testsuite/gdb.base/watchpoint.exp
gdb/testsuite/gdb.cp/classes.exp
gdb/testsuite/gdb.cp/local.exp
gdb/testsuite/gdb.cp/misc.cc
gdb/testsuite/gdb.cp/rtti.exp
gdb/testsuite/gdb.cp/rtti.h
gdb/testsuite/gdb.cp/rtti1.cc
gdb/testsuite/gdb.cp/rtti2.cc
gdb/testsuite/gdb.cp/templates.exp
gdb/trad-frame.c
gdb/trad-frame.h
gdb/tramp-frame.c
gdb/tramp-frame.h
gdb/tui/tui-data.c
gdb/tui/tui-data.h
gdb/tui/tui-layout.c
gdb/tui/tui-regs.c
gdb/tui/tui-regs.h
gdb/tui/tui-win.c
gdb/tui/tui-win.h
gdb/user-regs.c
gdb/v850-tdep.c
gdb/version.in
gdb/xstormy16-tdep.c
include/ChangeLog
include/bfdlink.h
include/elf/ChangeLog
include/elf/arm.h
include/elf/frv.h
include/elf/sh.h
include/opcode/ChangeLog
include/opcode/i386.h
include/opcode/ppc.h
libiberty/ChangeLog
libiberty/Makefile.in
libiberty/config.in
libiberty/configure
libiberty/configure.ac
libiberty/pex-common.h
libiberty/pex-unix.c
libiberty/testsuite/test-demangle.c
opcodes/ChangeLog
opcodes/aclocal.m4
opcodes/config.in
opcodes/configure
opcodes/frv-asm.c
opcodes/frv-desc.c
opcodes/frv-desc.h
opcodes/frv-dis.c
opcodes/frv-ibld.c
opcodes/frv-opc.c
opcodes/frv-opc.h
opcodes/i386-dis.c
opcodes/po/POTFILES.in
opcodes/po/de.po
opcodes/po/opcodes.pot
opcodes/ppc-dis.c
opcodes/ppc-opc.c
opcodes/sh-dis.c
opcodes/sh-opc.h
opcodes/sparc-dis.c
sim/ChangeLog
sim/MAINTAINERS
sim/frv/ChangeLog
sim/frv/Makefile.in
sim/frv/arch.c
sim/frv/arch.h
sim/frv/cache.c
sim/frv/cpu.h
sim/frv/cpuall.h
sim/frv/decode.c
sim/frv/decode.h
sim/frv/frv-sim.h
sim/frv/frv.c
sim/frv/interrupts.c
sim/frv/memory.c
sim/frv/mloop.in
sim/frv/model.c
sim/frv/profile-fr450.c
sim/frv/profile.c
sim/frv/registers.c
sim/frv/sem.c
sim/frv/traps.c
sim/testsuite/ChangeLog
sim/testsuite/sim/frv/allinsn.exp
sim/testsuite/sim/frv/fr400/addss.cgs
sim/testsuite/sim/frv/fr400/allinsn.exp
sim/testsuite/sim/frv/fr400/scutss.cgs
sim/testsuite/sim/frv/fr400/slass.cgs
sim/testsuite/sim/frv/fr400/smass.cgs
sim/testsuite/sim/frv/fr400/smsss.cgs
sim/testsuite/sim/frv/fr400/smu.cgs
sim/testsuite/sim/frv/fr400/subss.cgs
sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
sim/testsuite/sim/frv/interrupts/fp_exception.cgs
sim/testsuite/sim/frv/mqlclrhs.cgs
sim/testsuite/sim/frv/mqlmths.cgs
sim/testsuite/sim/frv/mqsllhi.cgs
sim/testsuite/sim/frv/mqsrahi.cgs
Delete:
gdb/amd64-linux-tdep.h
gdb/config/alpha/tm-fbsd.h
libiberty/acconfig.h
Diffstat (limited to 'sim')
38 files changed, 20458 insertions, 1841 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index dec01da..27aba57 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,7 @@ +2004-03-10 Ben Elliston <bje@gnu.org> + + * MAINTAINERS: Update my mail address. + 2004-01-26 Chris Demetriou <cgd@broadcom.com> * configure.in (mips*-*-*): Configure in testsuite. diff --git a/sim/MAINTAINERS b/sim/MAINTAINERS index 6e05721..1980b0d 100644 --- a/sim/MAINTAINERS +++ b/sim/MAINTAINERS @@ -16,7 +16,7 @@ ppc Andrew Cagney <ac131313@redhat.com> m68hc11 Stephane Carrez <stcarrez@nerim.fr> mips Chris Demetriou <cgd@broadcom.com> sh (global maintainers) -common Ben Elliston <bje@wasabisystems.com> +common Ben Elliston <bje@gnu.org> common Frank Ch. Eigler <fche@redhat.com> * (target, then global maintainers) diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog index 68b33ec..5c7c51d 100644 --- a/sim/frv/ChangeLog +++ b/sim/frv/ChangeLog @@ -1,3 +1,57 @@ +2004-03-01 Richard Sandiford <rsandifo@redhat.com> + + * Makefile.in (SIM_OBJS): Add profile-fr450.o. + (profile-fr450.o): New dependency. + (stamp-cpu): Add fr450 to the list of machs. + * sim-frv.h (SPR_IS_ACC): New macro. + (H_SPR_ACC4, H_SPR_ACC63, H_SPR_ACCG4, H_SPR_ACCG63): Delete. + * cache.c (frv_cache_init, non_cache_access): Handle bfd_mach_fr450. + * frv.c (check_register_alignment, check_fr_register_alignment) + (check_memory_alignment, do_media_average): Likewise. + (frvbf_clear_accumulators): Likewise. Use a mask of valid registers + rather than a consecutive range. + * interrupts.c (frv_queue_illegal_instruction_interrupt) + (frv_queue_non_implemented_instruction_interrupt): Handle + bfd_mach_fr450. + * memory.c (check_data_read_address, check_readwrite_address) + (check_insn_read_address, check_write_address): Likewise. + * mloop.in (@cpu@_simulate_insn_prefetch): Likewise. + * profile.c (reset_gr_flags, reset_fr_flags, reset_acc_flags) + (frvbf_model_insn_before, frvbf_model_insn_after): Likewise. + * profile-fr450.c: New file. + * registers.c (fr450_spr): New array. + (frv_register_control_init): Check its size. Use it for fr450. + (frv_check_register_access): Handle bfd_mach_fr450. + (frv_check_spr_read_access): Likewise. Generalize accumulator check. + * traps.c (frv_core_signal, frvbf_media_cr_not_aligned): Likewise. + (frvbf_media_acc_not_aligned): Likewise. + (frvbf_media_register_not_aligned): Likewise. + * arch.c: Regenerate. + * arch.h: Regenerate. + * cpu.h: Regenerate. + * cpuall.h: Regenerate. + * decode.h: Regenerate. + * model.c: Regenerate. + +2004-03-01 Richard Sandiford <rsandifo@redhat.com> + + * cache.c (frv_cache_init): Change fr400 cache statistics to match + the fr405. + (non_cache_access): Add missing breaks. + * interrupts.c (set_exception_status_registers): Always set EAR15 + for data_access_errors. + * memory.c (fr400_check_write_address): Remove redundant alignment + check. + * model.c: Regenerate. + +2004-03-01 Richard Sandiford <rsandifo@redhat.com> + + * frv.c (frvbf_iacc_cut): Rework, taking rounding into account. + +2004-03-01 Richard Sandiford <rsandifo@redhat.com> + + * decode.c, decode.h, model.c, sem.c: Regenerate. + 2003-11-24 Kevin Buettner <kevinb@redhat.com> * frv-sim.h (GR_REGNUM_MAX, FR_REGNUM_MAX, PC_REGNUM, SPR_REGNUM_MIN) diff --git a/sim/frv/Makefile.in b/sim/frv/Makefile.in index adc11ca..c2bcb36 100644 --- a/sim/frv/Makefile.in +++ b/sim/frv/Makefile.in @@ -35,7 +35,7 @@ SIM_OBJS = \ sim-if.o arch.o \ $(FRV_OBJS) \ traps.o interrupts.o memory.o cache.o pipeline.o \ - profile.o profile-fr400.o profile-fr500.o profile-fr550.o options.o \ + profile.o profile-fr400.o profile-fr450.o profile-fr500.o profile-fr550.o options.o \ devices.o reset.o registers.o \ $(CONFIG_DEVICES) @@ -80,6 +80,7 @@ reset.o: reset.c $(FRVBF_INCLUDE_DEPS) registers.o: registers.c $(FRVBF_INCLUDE_DEPS) profile.o: profile.c profile-fr400.h profile-fr500.h profile-fr550.h $(FRVBF_INCLUDE_DEPS) profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS) +profile-fr450.o: profile-fr450.c $(FRVBF_INCLUDE_DEPS) profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS) profile-fr550.o: profile-fr550.c profile-fr550.h $(FRVBF_INCLUDE_DEPS) sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h @@ -121,7 +122,7 @@ arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=frvbf mach=frv,fr550,fr500,fr400,tomcat,simple SUFFIX= \ + cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple SUFFIX= \ archfile=$(srcdir)/../../cpu/frv.cpu \ FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \ EXTRAFILES="$(CGEN_CPU_SEM)" diff --git a/sim/frv/arch.c b/sim/frv/arch.c index d0ac82f..de377bd 100644 --- a/sim/frv/arch.c +++ b/sim/frv/arch.c @@ -43,6 +43,9 @@ const MACH *sim_machs[] = & fr400_mach, #endif #ifdef HAVE_CPU_FRVBF + & fr450_mach, +#endif +#ifdef HAVE_CPU_FRVBF & simple_mach, #endif 0 diff --git a/sim/frv/arch.h b/sim/frv/arch.h index 6f26965..1d88201 100644 --- a/sim/frv/arch.h +++ b/sim/frv/arch.h @@ -30,7 +30,7 @@ with this program; if not, write to the Free Software Foundation, Inc., /* Enum declaration for model types. */ typedef enum model_type { MODEL_FRV, MODEL_FR550, MODEL_FR500, MODEL_TOMCAT - , MODEL_FR400, MODEL_SIMPLE, MODEL_MAX + , MODEL_FR400, MODEL_FR450, MODEL_SIMPLE, MODEL_MAX } MODEL_TYPE; #define MAX_MODELS ((int) MODEL_MAX) @@ -74,7 +74,19 @@ typedef enum unit_type { , UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE , UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP , UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER - , UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX + , UNIT_FR400_U_EXEC, UNIT_FR450_U_DCUL, UNIT_FR450_U_ICUL, UNIT_FR450_U_DCPL + , UNIT_FR450_U_ICPL, UNIT_FR450_U_DCF, UNIT_FR450_U_DCI, UNIT_FR450_U_ICI + , UNIT_FR450_U_MEMBAR, UNIT_FR450_U_BARRIER, UNIT_FR450_U_MEDIA_DUAL_HTOB, UNIT_FR450_U_MEDIA_DUAL_EXPAND + , UNIT_FR450_U_MEDIA_7, UNIT_FR450_U_MEDIA_6, UNIT_FR450_U_MEDIA_4_MCLRACCA, UNIT_FR450_U_MEDIA_4_ACC_DUAL + , UNIT_FR450_U_MEDIA_4_ACCG, UNIT_FR450_U_MEDIA_4, UNIT_FR450_U_MEDIA_3_QUAD, UNIT_FR450_U_MEDIA_3_DUAL + , UNIT_FR450_U_MEDIA_3, UNIT_FR450_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR450_U_MEDIA_2_ADD_SUB, UNIT_FR450_U_MEDIA_2_ACC_DUAL + , UNIT_FR450_U_MEDIA_2_ACC, UNIT_FR450_U_MEDIA_2_QUAD, UNIT_FR450_U_MEDIA_2, UNIT_FR450_U_MEDIA_HILO + , UNIT_FR450_U_MEDIA_1_QUAD, UNIT_FR450_U_MEDIA_1, UNIT_FR450_U_GR2SPR, UNIT_FR450_U_GR2FR + , UNIT_FR450_U_SPR2GR, UNIT_FR450_U_FR2GR, UNIT_FR450_U_SWAP, UNIT_FR450_U_FR_STORE + , UNIT_FR450_U_FR_LOAD, UNIT_FR450_U_GR_STORE, UNIT_FR450_U_GR_LOAD, UNIT_FR450_U_SET_HILO + , UNIT_FR450_U_CHECK, UNIT_FR450_U_TRAP, UNIT_FR450_U_BRANCH, UNIT_FR450_U_IDIV + , UNIT_FR450_U_IMUL, UNIT_FR450_U_INTEGER, UNIT_FR450_U_EXEC, UNIT_SIMPLE_U_EXEC + , UNIT_MAX } UNIT_TYPE; #define MAX_UNITS (1) diff --git a/sim/frv/cache.c b/sim/frv/cache.c index 7b2635b..0605682 100644 --- a/sim/frv/cache.c +++ b/sim/frv/cache.c @@ -38,8 +38,9 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: if (cache->configured_sets == 0) - cache->configured_sets = 128; + cache->configured_sets = 512; if (cache->configured_ways == 0) cache->configured_ways = 2; if (cache->line_size == 0) @@ -205,9 +206,11 @@ non_cache_access (FRV_CACHE *cache, USI address) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: if (address >= 0xff000000 || address >= 0xfe000000 && address <= 0xfeffffff) return 1; /* non-cache access */ + break; case bfd_mach_fr550: if (address >= 0xff000000 || address >= 0xfeff0000 && address <= 0xfeffffff) @@ -219,6 +222,7 @@ non_cache_access (FRV_CACHE *cache, USI address) } else if (address >= 0xfe400000 && address <= 0xfe407fff) return 1; /* non-cache access */ + break; default: if (address >= 0xff000000 || address >= 0xfeff0000 && address <= 0xfeffffff) @@ -230,6 +234,7 @@ non_cache_access (FRV_CACHE *cache, USI address) } else if (address >= 0xfe400000 && address <= 0xfe403fff) return 1; /* non-cache access */ + break; } hsr0 = GET_HSR0 (); diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h index 6325368..6257267 100644 --- a/sim/frv/cpu.h +++ b/sim/frv/cpu.h @@ -398,6 +398,19 @@ typedef struct { } MODEL_FR400_DATA; typedef struct { + DI prev_fp_load; + DI prev_fr_p4; + DI prev_fr_p6; + DI prev_acc_p2; + DI prev_acc_p4; + DI cur_fp_load; + DI cur_fr_p4; + DI cur_fr_p6; + DI cur_acc_p2; + DI cur_acc_p4; +} MODEL_FR450_DATA; + +typedef struct { int empty; } MODEL_SIMPLE_DATA; @@ -1263,6 +1276,23 @@ union sem_fields { } sfmt_cmaddhss; struct { /* */ UINT f_FRi; + UINT f_FRk; + UINT f_u6; + unsigned char in_FRintieven; + unsigned char in_FRintkeven; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char out_FRintieven; + unsigned char out_FRintkeven; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + } sfmt_mqsllhi; + struct { /* */ + UINT f_FRi; UINT f_FRj; UINT f_FRk; unsigned char in_FRi; @@ -3149,6 +3179,50 @@ struct scache { f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ +#define EXTRACT_IFMT_LRAI_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_LRAE; \ + UINT f_LRAD; \ + UINT f_LRAS; \ + UINT f_LRA_null; \ + unsigned int length; +#define EXTRACT_IFMT_LRAI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_LRAE = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \ + f_LRAD = EXTRACT_LSB0_UINT (insn, 32, 4, 1); \ + f_LRAS = EXTRACT_LSB0_UINT (insn, 32, 3, 1); \ + f_LRA_null = EXTRACT_LSB0_UINT (insn, 32, 2, 3); \ + +#define EXTRACT_IFMT_TLBPR_VARS \ + UINT f_pack; \ + UINT f_TLBPR_null; \ + UINT f_TLBPRopx; \ + UINT f_TLBPRL; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_TLBPR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_TLBPR_null = EXTRACT_LSB0_UINT (insn, 32, 30, 2); \ + f_TLBPRopx = EXTRACT_LSB0_UINT (insn, 32, 28, 3); \ + f_TLBPRL = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + #define EXTRACT_IFMT_COP1_VARS \ UINT f_pack; \ UINT f_CPRk; \ @@ -3836,6 +3910,23 @@ struct scache { f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ +#define EXTRACT_IFMT_MQSLLHI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_u6; \ + unsigned int length; +#define EXTRACT_IFMT_MQSLLHI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + #define EXTRACT_IFMT_MADDACCS_VARS \ UINT f_pack; \ UINT f_ACC40Sk; \ diff --git a/sim/frv/cpuall.h b/sim/frv/cpuall.h index 4d1cb68..44b52b3 100644 --- a/sim/frv/cpuall.h +++ b/sim/frv/cpuall.h @@ -39,6 +39,7 @@ extern const MACH fr550_mach; extern const MACH fr500_mach; extern const MACH tomcat_mach; extern const MACH fr400_mach; +extern const MACH fr450_mach; extern const MACH simple_mach; #ifndef WANT_CPU diff --git a/sim/frv/decode.c b/sim/frv/decode.c index ef6be5a..620cbdf 100644 --- a/sim/frv/decode.c +++ b/sim/frv/decode.c @@ -223,22 +223,12 @@ static const struct insn_sem frvbf_insn_sem[] = { FRV_INSN_STHF, FRVBF_INSN_STHF, FRVBF_SFMT_STBF }, { FRV_INSN_STF, FRVBF_INSN_STF, FRVBF_SFMT_STBF }, { FRV_INSN_STC, FRVBF_INSN_STC, FRVBF_SFMT_STC }, - { FRV_INSN_RSTB, FRVBF_INSN_RSTB, FRVBF_SFMT_RSTB }, - { FRV_INSN_RSTH, FRVBF_INSN_RSTH, FRVBF_SFMT_RSTB }, - { FRV_INSN_RST, FRVBF_INSN_RST, FRVBF_SFMT_RSTB }, - { FRV_INSN_RSTBF, FRVBF_INSN_RSTBF, FRVBF_SFMT_RSTBF }, - { FRV_INSN_RSTHF, FRVBF_INSN_RSTHF, FRVBF_SFMT_RSTBF }, - { FRV_INSN_RSTF, FRVBF_INSN_RSTF, FRVBF_SFMT_RSTBF }, { FRV_INSN_STD, FRVBF_INSN_STD, FRVBF_SFMT_STD }, { FRV_INSN_STDF, FRVBF_INSN_STDF, FRVBF_SFMT_STDF }, { FRV_INSN_STDC, FRVBF_INSN_STDC, FRVBF_SFMT_STDC }, - { FRV_INSN_RSTD, FRVBF_INSN_RSTD, FRVBF_SFMT_RSTD }, - { FRV_INSN_RSTDF, FRVBF_INSN_RSTDF, FRVBF_SFMT_RSTDF }, { FRV_INSN_STQ, FRVBF_INSN_STQ, FRVBF_SFMT_LDQ }, { FRV_INSN_STQF, FRVBF_INSN_STQF, FRVBF_SFMT_LDQF }, { FRV_INSN_STQC, FRVBF_INSN_STQC, FRVBF_SFMT_LDQC }, - { FRV_INSN_RSTQ, FRVBF_INSN_RSTQ, FRVBF_SFMT_LDQ }, - { FRV_INSN_RSTQF, FRVBF_INSN_RSTQF, FRVBF_SFMT_LDQF }, { FRV_INSN_STBU, FRVBF_INSN_STBU, FRVBF_SFMT_STBU }, { FRV_INSN_STHU, FRVBF_INSN_STHU, FRVBF_SFMT_STBU }, { FRV_INSN_STU, FRVBF_INSN_STU, FRVBF_SFMT_STBU }, @@ -578,6 +568,9 @@ static const struct insn_sem frvbf_insn_sem[] = { FRV_INSN_DCUL, FRVBF_INSN_DCUL, FRVBF_SFMT_ICUL }, { FRV_INSN_BAR, FRVBF_INSN_BAR, FRVBF_SFMT_REI }, { FRV_INSN_MEMBAR, FRVBF_INSN_MEMBAR, FRVBF_SFMT_REI }, + { FRV_INSN_LRAI, FRVBF_INSN_LRAI, FRVBF_SFMT_REI }, + { FRV_INSN_LRAD, FRVBF_INSN_LRAD, FRVBF_SFMT_REI }, + { FRV_INSN_TLBPR, FRVBF_INSN_TLBPR, FRVBF_SFMT_REI }, { FRV_INSN_COP1, FRVBF_INSN_COP1, FRVBF_SFMT_REI }, { FRV_INSN_COP2, FRVBF_INSN_COP2, FRVBF_SFMT_REI }, { FRV_INSN_CLRGR, FRVBF_INSN_CLRGR, FRVBF_SFMT_CLRGR }, @@ -725,6 +718,10 @@ static const struct insn_sem frvbf_insn_sem[] = { FRV_INSN_CMQADDHUS, FRVBF_INSN_CMQADDHUS, FRVBF_SFMT_CMQADDHSS }, { FRV_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHSS, FRVBF_SFMT_CMQADDHSS }, { FRV_INSN_CMQSUBHUS, FRVBF_INSN_CMQSUBHUS, FRVBF_SFMT_CMQADDHSS }, + { FRV_INSN_MQLCLRHS, FRVBF_INSN_MQLCLRHS, FRVBF_SFMT_MQSATHS }, + { FRV_INSN_MQLMTHS, FRVBF_INSN_MQLMTHS, FRVBF_SFMT_MQSATHS }, + { FRV_INSN_MQSLLHI, FRVBF_INSN_MQSLLHI, FRVBF_SFMT_MQSLLHI }, + { FRV_INSN_MQSRAHI, FRVBF_INSN_MQSRAHI, FRVBF_SFMT_MQSLLHI }, { FRV_INSN_MADDACCS, FRVBF_INSN_MADDACCS, FRVBF_SFMT_MADDACCS }, { FRV_INSN_MSUBACCS, FRVBF_INSN_MSUBACCS, FRVBF_SFMT_MADDACCS }, { FRV_INSN_MDADDACCS, FRVBF_INSN_MDADDACCS, FRVBF_SFMT_MDADDACCS }, @@ -1014,19 +1011,12 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, case 26 : itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu; case 27 : itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu; case 28 : itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu; - case 32 : itype = FRVBF_INSN_RSTB; goto extract_sfmt_rstb; - case 33 : itype = FRVBF_INSN_RSTH; goto extract_sfmt_rstb; - case 34 : itype = FRVBF_INSN_RST; goto extract_sfmt_rstb; - case 35 : itype = FRVBF_INSN_RSTD; goto extract_sfmt_rstd; - case 36 : itype = FRVBF_INSN_RSTQ; goto extract_sfmt_ldq; + case 32 : itype = FRVBF_INSN_LRAI; goto extract_sfmt_rei; + case 33 : itype = FRVBF_INSN_LRAD; goto extract_sfmt_rei; + case 36 : itype = FRVBF_INSN_TLBPR; goto extract_sfmt_rei; case 37 : itype = FRVBF_INSN_STC; goto extract_sfmt_stc; case 38 : itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc; case 39 : itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc; - case 40 : itype = FRVBF_INSN_RSTBF; goto extract_sfmt_rstbf; - case 41 : itype = FRVBF_INSN_RSTHF; goto extract_sfmt_rstbf; - case 42 : itype = FRVBF_INSN_RSTF; goto extract_sfmt_rstbf; - case 43 : itype = FRVBF_INSN_RSTDF; goto extract_sfmt_rstdf; - case 44 : itype = FRVBF_INSN_RSTQF; goto extract_sfmt_ldqf; case 45 : itype = FRVBF_INSN_STCU; goto extract_sfmt_stcu; case 46 : itype = FRVBF_INSN_STDCU; goto extract_sfmt_stdcu; case 47 : itype = FRVBF_INSN_STQCU; goto extract_sfmt_ldqcu; @@ -1858,7 +1848,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 120 : { - unsigned int val = (((insn >> 7) & (1 << 4)) | ((insn >> 6) & (15 << 0))); + unsigned int val = (((insn >> 6) & (63 << 0))); switch (val) { case 0 : itype = FRVBF_INSN_MQXMACHS; goto extract_sfmt_mqmachs; @@ -1876,12 +1866,16 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, case 13 : itype = FRVBF_INSN_MCPLI; goto extract_sfmt_mcpli; case 14 : itype = FRVBF_INSN_MDCUTSSI; goto extract_sfmt_mdcutssi; case 15 : itype = FRVBF_INSN_MQSATHS; goto extract_sfmt_mqsaths; - case 16 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos; - case 17 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh; - case 18 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis; - case 19 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih; - case 20 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets; - case 21 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth; + case 16 : itype = FRVBF_INSN_MQLCLRHS; goto extract_sfmt_mqsaths; + case 17 : itype = FRVBF_INSN_MQSLLHI; goto extract_sfmt_mqsllhi; + case 19 : itype = FRVBF_INSN_MQSRAHI; goto extract_sfmt_mqsllhi; + case 20 : itype = FRVBF_INSN_MQLMTHS; goto extract_sfmt_mqsaths; + case 32 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos; + case 33 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh; + case 34 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis; + case 35 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih; + case 36 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets; + case 37 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth; default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; } } @@ -4617,70 +4611,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_sfmt_rstb: - { - const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_cswap.f - UINT f_GRk; - UINT f_GRi; - UINT f_GRj; - - f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); - f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); - f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); - - /* Record the fields for the semantic handler. */ - FLD (f_GRi) = f_GRi; - FLD (f_GRj) = f_GRj; - FLD (f_GRk) = f_GRk; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_GRi) = f_GRi; - FLD (in_GRj) = f_GRj; - FLD (in_GRk) = f_GRk; - } -#endif -#undef FLD - return idesc; - } - - extract_sfmt_rstbf: - { - const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_cstbfu.f - UINT f_FRk; - UINT f_GRi; - UINT f_GRj; - - f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); - f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); - f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); - - /* Record the fields for the semantic handler. */ - FLD (f_FRk) = f_FRk; - FLD (f_GRi) = f_GRi; - FLD (f_GRj) = f_GRj; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstbf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_FRintk) = f_FRk; - FLD (in_GRi) = f_GRi; - FLD (in_GRj) = f_GRj; - } -#endif -#undef FLD - return idesc; - } - extract_sfmt_std: { const IDESC *idesc = &frvbf_insn_data[itype]; @@ -4777,70 +4707,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_sfmt_rstd: - { - const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_cstdu.f - UINT f_GRk; - UINT f_GRi; - UINT f_GRj; - - f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); - f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); - f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); - - /* Record the fields for the semantic handler. */ - FLD (f_GRk) = f_GRk; - FLD (f_GRi) = f_GRi; - FLD (f_GRj) = f_GRj; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstd", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_GRdoublek) = f_GRk; - FLD (in_GRi) = f_GRi; - FLD (in_GRj) = f_GRj; - } -#endif -#undef FLD - return idesc; - } - - extract_sfmt_rstdf: - { - const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_cstdfu.f - UINT f_FRk; - UINT f_GRi; - UINT f_GRj; - - f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); - f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); - f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); - - /* Record the fields for the semantic handler. */ - FLD (f_FRk) = f_FRk; - FLD (f_GRi) = f_GRi; - FLD (f_GRj) = f_GRj; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstdf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_FRdoublek) = f_FRk; - FLD (in_GRi) = f_GRi; - FLD (in_GRj) = f_GRj; - } -#endif -#undef FLD - return idesc; - } - extract_sfmt_stbu: { const IDESC *idesc = &frvbf_insn_data[itype]; @@ -9607,6 +9473,47 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } + extract_sfmt_mqsllhi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + UINT f_FRk; + UINT f_FRi; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRk) = f_FRk; + FLD (f_u6) = f_u6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqsllhi", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (out_FRintieven) = f_FRi; + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + extract_sfmt_maddaccs: { const IDESC *idesc = &frvbf_insn_data[itype]; diff --git a/sim/frv/decode.h b/sim/frv/decode.h index 9741d36..e1f1cd4 100644 --- a/sim/frv/decode.h +++ b/sim/frv/decode.h @@ -79,150 +79,149 @@ typedef enum frvbf_insn_type { , FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI, FRVBF_INSN_NLDDI , FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI, FRVBF_INSN_NLDQFI , FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST, FRVBF_INSN_STBF - , FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_RSTB - , FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF - , FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF, FRVBF_INSN_STDC - , FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ, FRVBF_INSN_STQF - , FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF, FRVBF_INSN_STBU - , FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU, FRVBF_INSN_STHFU - , FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU, FRVBF_INSN_STDFU - , FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU, FRVBF_INSN_STQCU - , FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH - , FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF - , FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU - , FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU - , FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU - , FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB, FRVBF_INSN_CSTH - , FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF - , FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU - , FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU - , FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI - , FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI, FRVBF_INSN_STHFI - , FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI, FRVBF_INSN_STQI - , FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP - , FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD - , FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG - , FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG - , FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ, FRVBF_INSN_BNE - , FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT, FRVBF_INSN_BGE - , FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC, FRVBF_INSN_BNC - , FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV, FRVBF_INSN_BNV - , FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ - , FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL, FRVBF_INSN_FBGE - , FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG, FRVBF_INSN_FBLE - , FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU, FRVBF_INSN_FBO - , FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR - , FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR - , FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR, FRVBF_INSN_BCLR - , FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR, FRVBF_INSN_BVLR - , FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR - , FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR - , FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR - , FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR - , FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR - , FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR - , FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR - , FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR - , FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR - , FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR - , FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR - , FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR - , FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL - , FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT, FRVBF_INSN_REI - , FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ, FRVBF_INSN_TNE - , FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT, FRVBF_INSN_TGE - , FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC, FRVBF_INSN_TNC - , FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV, FRVBF_INSN_TNV - , FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ - , FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL, FRVBF_INSN_FTGE - , FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG, FRVBF_INSN_FTLE - , FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU, FRVBF_INSN_FTO - , FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ, FRVBF_INSN_TINE - , FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT, FRVBF_INSN_TIGE - , FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC, FRVBF_INSN_TINC - , FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV, FRVBF_INSN_TINV - , FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ - , FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE - , FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE - , FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU, FRVBF_INSN_FTIO - , FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR - , FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR - , FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR - , FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE - , FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT, FRVBF_INSN_CKGE - , FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC, FRVBF_INSN_CKNC - , FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV, FRVBF_INSN_CKNV - , FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ - , FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE - , FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE - , FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU, FRVBF_INSN_FCKO - , FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE - , FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE - , FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC - , FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV - , FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ - , FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE - , FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE - , FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO - , FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI, FRVBF_INSN_DCI - , FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF, FRVBF_INSN_DCEF - , FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI - , FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL - , FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1, FRVBF_INSN_COP2 - , FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA - , FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA - , FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI - , FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI - , FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI - , FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS - , FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS - , FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS - , FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD - , FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS - , FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD - , FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS - , FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS - , FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD - , FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS - , FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS - , FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS - , FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS - , FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS - , FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS - , FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS - , FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS - , FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS - , FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS - , FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND - , FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND, FRVBF_INSN_CMOR - , FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI - , FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT - , FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI - , FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI - , FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS - , FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH - , FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS - , FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS - , FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS - , FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS - , FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS - , FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS - , FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS - , FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS - , FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS - , FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS - , FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS - , FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS - , FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU - , FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU - , FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU - , FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD - , FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH - , FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB - , FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0 - , FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC - , FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP - , FRVBF_INSN__MAX + , FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_STD + , FRVBF_INSN_STDF, FRVBF_INSN_STDC, FRVBF_INSN_STQ, FRVBF_INSN_STQF + , FRVBF_INSN_STQC, FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU + , FRVBF_INSN_STBFU, FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU + , FRVBF_INSN_STDU, FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU + , FRVBF_INSN_STQFU, FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB + , FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF + , FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF + , FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU + , FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU + , FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU + , FRVBF_INSN_CSTB, FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF + , FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF + , FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU + , FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU + , FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI + , FRVBF_INSN_STBFI, FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI + , FRVBF_INSN_STDFI, FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP + , FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG + , FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ + , FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD + , FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO + , FRVBF_INSN_BEQ, FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT + , FRVBF_INSN_BLT, FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI + , FRVBF_INSN_BC, FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP + , FRVBF_INSN_BV, FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO + , FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE + , FRVBF_INSN_FBUL, FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE + , FRVBF_INSN_FBUG, FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE + , FRVBF_INSN_FBU, FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR + , FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR + , FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR + , FRVBF_INSN_BHILR, FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR + , FRVBF_INSN_BPLR, FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR + , FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR + , FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR + , FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR + , FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR + , FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR + , FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR + , FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR + , FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR + , FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR + , FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR + , FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR + , FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL + , FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL + , FRVBF_INSN_RETT, FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO + , FRVBF_INSN_TEQ, FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT + , FRVBF_INSN_TLT, FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI + , FRVBF_INSN_TC, FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP + , FRVBF_INSN_TV, FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO + , FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE + , FRVBF_INSN_FTUL, FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE + , FRVBF_INSN_FTUG, FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE + , FRVBF_INSN_FTU, FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO + , FRVBF_INSN_TIEQ, FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT + , FRVBF_INSN_TILT, FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI + , FRVBF_INSN_TIC, FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP + , FRVBF_INSN_TIV, FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO + , FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE + , FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE + , FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE + , FRVBF_INSN_FTIU, FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP + , FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR + , FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR + , FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO + , FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT + , FRVBF_INSN_CKLT, FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI + , FRVBF_INSN_CKC, FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP + , FRVBF_INSN_CKV, FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO + , FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE + , FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE + , FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE + , FRVBF_INSN_FCKU, FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO + , FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT + , FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI + , FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP + , FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO + , FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE + , FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE + , FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE + , FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL + , FRVBF_INSN_ICI, FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI + , FRVBF_INSN_DCF, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB + , FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL + , FRVBF_INSN_ICUL, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR + , FRVBF_INSN_LRAI, FRVBF_INSN_LRAD, FRVBF_INSN_TLBPR, FRVBF_INSN_COP1 + , FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA + , FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA + , FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD + , FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS + , FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS + , FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS + , FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS + , FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS + , FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS + , FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS + , FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD + , FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS + , FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS + , FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS + , FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS + , FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS + , FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS + , FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS + , FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS + , FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS + , FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS + , FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS + , FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS + , FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS + , FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH + , FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND + , FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT + , FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI + , FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI + , FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI + , FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI + , FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH + , FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS + , FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS + , FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS + , FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS + , FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MQLCLRHS, FRVBF_INSN_MQLMTHS + , FRVBF_INSN_MQSLLHI, FRVBF_INSN_MQSRAHI, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS + , FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS + , FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU + , FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU + , FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU + , FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU + , FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU + , FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS + , FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS + , FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS + , FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS + , FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD + , FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH + , FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB + , FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP + , FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG + , FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2 + , FRVBF_INSN_FNOP, FRVBF_INSN__MAX } FRVBF_INSN_TYPE; /* Enum declaration for semantic formats in cpu family frvbf. */ @@ -245,8 +244,7 @@ typedef enum frvbf_sfmt_type { , FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI, FRVBF_SFMT_LDDI , FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI, FRVBF_SFMT_LDQI , FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB, FRVBF_SFMT_STBF - , FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD - , FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF + , FRVBF_SFMT_STC, FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC , FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU, FRVBF_SFMT_STDU , FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB , FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ @@ -283,16 +281,17 @@ typedef enum frvbf_sfmt_type { , FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI , FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI , FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS - , FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS - , FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS - , FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU - , FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU - , FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS - , FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD - , FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH - , FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB - , FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0 - , FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG + , FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MQSLLHI, FRVBF_SFMT_MADDACCS + , FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS + , FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS + , FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS + , FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS + , FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW + , FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH + , FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH + , FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE + , FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC + , FRVBF_SFMT_MWTACCG } FRVBF_SFMT_TYPE; /* Function unit handlers (user written). */ @@ -445,6 +444,52 @@ extern int frvbf_model_fr400_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, extern int frvbf_model_fr400_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/); extern int frvbf_model_fr400_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); extern int frvbf_model_fr400_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr450_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_membar (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr450_u_barrier (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr450_u_media_dual_htob (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_7 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FCCk*/); +extern int frvbf_model_fr450_u_media_6 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_4_accg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACCGi*/, INT /*FRinti*/, INT /*ACCGk*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_3_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_3_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_3 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr450_u_media_2_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr450_u_media_2_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr450_u_media_2 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr450_u_media_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRkhi*/, INT /*FRklo*/); +extern int frvbf_model_fr450_u_media_1_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_1 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/); +extern int frvbf_model_fr450_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/); +extern int frvbf_model_fr450_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr450_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr450_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr450_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr450_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/); +extern int frvbf_model_fr450_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/); +extern int frvbf_model_fr450_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr450_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr450_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr450_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/); +extern int frvbf_model_fr450_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr450_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); extern int frvbf_model_simple_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); /* Profiling before/after handlers (user written) */ diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h index 39da19c..ce5d492 100644 --- a/sim/frv/frv-sim.h +++ b/sim/frv/frv-sim.h @@ -23,11 +23,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "sim-options.h" -/* Not defined in the cgen cpu file for access restriction purposes. */ -#define H_SPR_ACC4 1412 -#define H_SPR_ACC63 1471 -#define H_SPR_ACCG4 1476 -#define H_SPR_ACCG63 1535 +/* True if SPR is the number of accumulator or accumulator guard register. */ +#define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535) /* Initialization of the frv cpu. */ void frv_initialize (SIM_CPU *, SIM_DESC); diff --git a/sim/frv/frv.c b/sim/frv/frv.c index de1ff1d..e82f3d0 100644 --- a/sim/frv/frv.c +++ b/sim/frv/frv.c @@ -1,5 +1,6 @@ /* frv simulator support code - Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Copyright (C) 1998, 1999, 2000, 2001, 2003, 2004 Free Software + Foundation, Inc. Contributed by Red Hat. This file is part of the GNU simulators. @@ -172,7 +173,15 @@ check_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask) SIM_DESC sd = CPU_STATE (current_cpu); switch (STATE_ARCHITECTURE (sd)->mach) { + /* Note: there is a discrepancy between V2.2 of the FR400 + instruction manual and the various FR4xx LSI specs. + The former claims that unaligned registers cause a + register_exception while the latter say it's an + illegal_instruction. The LSI specs appear to be + correct; in fact, the FR4xx series is not documented + as having a register_exception. */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; @@ -200,7 +209,9 @@ check_fr_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask) SIM_DESC sd = CPU_STATE (current_cpu); switch (STATE_ARCHITECTURE (sd)->mach) { + /* See comment in check_register_alignment(). */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; @@ -232,7 +243,9 @@ check_memory_alignment (SIM_CPU *current_cpu, SI address, int align_mask) SIM_DESC sd = CPU_STATE (current_cpu); switch (STATE_ARCHITECTURE (sd)->mach) { + /* See comment in check_register_alignment(). */ case bfd_mach_fr400: + case bfd_mach_fr450: frv_queue_data_access_error_interrupt (current_cpu, address); break; case bfd_mach_frvtomcat: @@ -989,10 +1002,11 @@ void frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A) { SIM_DESC sd = CPU_STATE (current_cpu); - int acc_num = - (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 8 : - (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 8 : - (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 4 : + int acc_mask = + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 7 : + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 7 : + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) ? 11 : + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 3 : 63; FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); @@ -1002,15 +1016,16 @@ frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A) { /* This instruction is a nop if the referenced accumulator is not implemented. */ - if (acc_ix < acc_num) + if ((acc_ix & acc_mask) == acc_ix) sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, acc_ix, 0); } else { /* Clear all implemented accumulators. */ int i; - for (i = 0; i < acc_num; ++i) - sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0); + for (i = 0; i <= acc_mask; ++i) + if ((i & acc_mask) == i) + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0); } } @@ -1100,25 +1115,53 @@ frvbf_media_cut_ss (SIM_CPU *current_cpu, DI acc, SI cut_point) SI frvbf_iacc_cut (SIM_CPU *current_cpu, DI acc, SI cut_point) { - /* The cut point is the lower 6 bits (signed) of what we are passed. */ + DI lower, upper; + + /* The cut point is the lower 7 bits (signed) of what we are passed. */ cut_point = cut_point << 25 >> 25; - if (cut_point <= -32) - cut_point = -31; /* Special case for full shiftout. */ + /* Conceptually, the operation is on a 128-bit sign-extension of ACC. + The top bit of the return value corresponds to bit (63 - CUT_POINT) + of this 128-bit value. - /* Negative cuts (cannot saturate). */ + Since we can't deal with 128-bit values very easily, convert the + operation into an equivalent 64-bit one. */ if (cut_point < 0) - return acc >> (32 + -cut_point); + { + /* Avoid an undefined shift operation. */ + if (cut_point == -64) + acc >>= 63; + else + acc >>= -cut_point; + cut_point = 0; + } - /* Positive cuts will saturate if significant bits are shifted out. */ - if (acc != ((acc << cut_point) >> cut_point)) - if (acc >= 0) - return 0x7fffffff; - else - return 0x80000000; + /* Get the shifted but unsaturated result. Set LOWER to the lowest + 32 bits of the result and UPPER to the result >> 31. */ + if (cut_point < 32) + { + /* The cut loses the (32 - CUT_POINT) least significant bits. + Round the result up if the most significant of these lost bits + is 1. */ + lower = acc >> (32 - cut_point); + if (lower < 0x7fffffff) + if (acc & LSBIT64 (32 - cut_point - 1)) + lower++; + upper = lower >> 31; + } + else + { + lower = acc << (cut_point - 32); + upper = acc >> (63 - cut_point); + } - /* No saturate, just cut. */ - return ((acc << cut_point) >> 32); + /* Saturate the result. */ + if (upper < -1) + return ~0x7fffffff; + else if (upper > 0) + return 0x7fffffff; + else + return lower; } /* Compute the result of shift-left-arithmetic-with-saturation (SLASS). */ @@ -1179,12 +1222,14 @@ do_media_average (SIM_CPU *current_cpu, HI arg1, HI arg2) HI result = sum >> 1; int rounding_value; - /* On fr400 and fr550, check the rounding mode. On other machines rounding is always - toward negative infinity and the result is already correctly rounded. */ + /* On fr4xx and fr550, check the rounding mode. On other machines + rounding is always toward negative infinity and the result is + already correctly rounded. */ switch (STATE_ARCHITECTURE (sd)->mach) { /* Need to check rounding mode. */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: /* Check whether rounding will be required. Rounding will be required if the sum is an odd number. */ diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c index 540ee06..6c40f1d 100644 --- a/sim/frv/interrupts.c +++ b/sim/frv/interrupts.c @@ -239,6 +239,7 @@ frv_queue_illegal_instruction_interrupt ( switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: break; default: @@ -299,6 +300,7 @@ frv_queue_non_implemented_instruction_interrupt ( switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: break; default: @@ -845,8 +847,7 @@ set_exception_status_registers ( break; case FRV_DATA_ACCESS_ERROR: reg_index = 15; /* Use ESR15, EPCR15. */ - if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400) - set_ear = 1; + set_ear = 1; break; case FRV_DATA_ACCESS_EXCEPTION: set_daec = 1; diff --git a/sim/frv/memory.c b/sim/frv/memory.c index 4dbc652..2249904 100644 --- a/sim/frv/memory.c +++ b/sim/frv/memory.c @@ -73,6 +73,7 @@ check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: address = fr400_check_data_read_address (current_cpu, address, align_mask); break; @@ -149,6 +150,7 @@ check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: address = fr400_check_readwrite_address (current_cpu, address, align_mask); break; @@ -240,6 +242,7 @@ check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: address = fr400_check_insn_read_address (current_cpu, address, align_mask); break; @@ -679,18 +682,6 @@ frvbf_read_imem_USI (SIM_CPU *current_cpu, PCADDR vpc) static SI fr400_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask) { - if (address & align_mask) - { - /* On the fr400, this causes a data_access_error. */ - /* Make sure that this exception is not masked. */ - USI isr = GET_ISR (); - if (! GET_ISR_EMAM (isr)) - { - /* Bad alignment causes a data_access_error on fr400. */ - frv_queue_data_access_error_interrupt (current_cpu, address); - } - address &= ~align_mask; - } if (align_mask == 7 && address >= 0xfe800000 && address <= 0xfeffffff) frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR); @@ -735,6 +726,7 @@ check_write_address (SIM_CPU *current_cpu, SI address, int align_mask) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: address = fr400_check_write_address (current_cpu, address, align_mask); break; case bfd_mach_frvtomcat: diff --git a/sim/frv/mloop.in b/sim/frv/mloop.in index 073d81d..24c34c9 100644 --- a/sim/frv/mloop.in +++ b/sim/frv/mloop.in @@ -391,6 +391,7 @@ static void switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: simulate_dual_insn_prefetch (current_cpu, vpc, 8); break; case bfd_mach_frvtomcat: diff --git a/sim/frv/model.c b/sim/frv/model.c index 864c180..17dae31 100644 --- a/sim/frv/model.c +++ b/sim/frv/model.c @@ -2867,102 +2867,6 @@ model_frv_stc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_frv_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_frv_std (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstdu.f @@ -3011,38 +2915,6 @@ model_frv_stdc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_frv_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_frv_stq (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_smulcc.f @@ -3091,38 +2963,6 @@ model_frv_stqc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_frv_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_frv_stbu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstbu.f @@ -8547,6 +8387,54 @@ model_frv_membar (SIM_CPU *current_cpu, void *sem_arg) } static int +model_frv_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_frv_cop1 (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -10899,6 +10787,70 @@ model_frv_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) } static int +model_frv_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_frv_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_mdasaccs.f @@ -16253,102 +16205,6 @@ model_fr550_stc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr550_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_fr550_std (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstdu.f @@ -16417,38 +16273,6 @@ model_fr550_stdc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr550_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_fr550_stq (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_smulcc.f @@ -16497,38 +16321,6 @@ model_fr550_stqc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr550_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_fr550_stbu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstbu.f @@ -20583,7 +20375,16 @@ model_fr550_calll (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); } return cycles; #undef FLD @@ -20622,7 +20423,14 @@ model_fr550_callil (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); } return cycles; #undef FLD @@ -23744,7 +23552,16 @@ model_fr550_ccalll (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); } return cycles; #undef FLD @@ -24063,6 +23880,54 @@ model_fr550_membar (SIM_CPU *current_cpu, void *sem_arg) } static int +model_fr550_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_fr550_cop1 (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -27354,6 +27219,70 @@ model_fr550_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) } static int +model_fr550_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_fr550_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_mdasaccs.f @@ -33251,162 +33180,6 @@ model_fr500_stc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr500_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_GRk = FLD (in_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_GRk = FLD (in_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_GRk = FLD (in_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_FRintk = FLD (in_FRintk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_FRintk = FLD (in_FRintk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_FRintk = FLD (in_FRintk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - -static int model_fr500_std (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstdu.f @@ -33475,58 +33248,6 @@ model_fr500_stdc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr500_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_GRdoublek = FLD (in_GRdoublek); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 3; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_FRdoublek = FLD (in_FRdoublek); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 3; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - -static int model_fr500_stq (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_smulcc.f @@ -33591,54 +33312,6 @@ model_fr500_stqc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr500_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - referenced |= 1 << 0; - referenced |= 1 << 1; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - referenced |= 1 << 0; - referenced |= 1 << 1; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - -static int model_fr500_stbu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstbu.f @@ -41224,6 +40897,54 @@ model_fr500_membar (SIM_CPU *current_cpu, void *sem_arg) } static int +model_fr500_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_fr500_cop1 (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -44864,6 +44585,70 @@ model_fr500_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) } static int +model_fr500_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_fr500_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_mdasaccs.f @@ -49218,102 +49003,6 @@ model_tomcat_stc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_tomcat_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_tomcat_std (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstdu.f @@ -49362,38 +49051,6 @@ model_tomcat_stdc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_tomcat_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_tomcat_stq (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_smulcc.f @@ -49442,38 +49099,6 @@ model_tomcat_stqc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_tomcat_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_tomcat_stbu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstbu.f @@ -54898,6 +54523,54 @@ model_tomcat_membar (SIM_CPU *current_cpu, void *sem_arg) } static int +model_tomcat_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_tomcat_cop1 (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -57250,6 +56923,70 @@ model_tomcat_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) } static int +model_tomcat_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_tomcat_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_mdasaccs.f @@ -58511,17 +58248,7 @@ model_fr400_nsdiv (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -58563,17 +58290,7 @@ model_fr400_nudiv (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -60003,15 +59720,7 @@ model_fr400_nsdivi (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -60051,15 +59760,7 @@ model_fr400_nudivi (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -62368,102 +62069,6 @@ model_fr400_stc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr400_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_fr400_std (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstdu.f @@ -62532,38 +62137,6 @@ model_fr400_stdc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr400_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_fr400_stq (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_smulcc.f @@ -62612,38 +62185,6 @@ model_fr400_stqc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr400_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_fr400_stbu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstbu.f @@ -70201,6 +69742,54 @@ model_fr400_membar (SIM_CPU *current_cpu, void *sem_arg) } static int +model_fr400_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_fr400_cop1 (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -72913,6 +72502,70 @@ model_fr400_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) } static int +model_fr400_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_fr400_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_mdasaccs.f @@ -74437,6 +74090,16051 @@ model_fr400_fnop (SIM_CPU *current_cpu, void *sem_arg) } static int +model_fr450_add (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_and (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_or (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_not (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nsdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_udiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_umul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smsss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_slass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_scutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_scan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cadd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csmul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csrl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cscan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_umulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_caddcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csubcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csmulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_csmulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_candcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_corcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cxorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csrlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nsdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_udivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nudivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_umuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_slli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_scani (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_oricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xoricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_umulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sllicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srlicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sraicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmpb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmpba (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_setlo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRklo = FLD (out_GRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_sethi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRkhi = FLD (out_GRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_setlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + out_GRk = FLD (out_GRk); + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_st (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_std (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_swap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_swapi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cswap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movgfq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgfq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movfgq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movfgq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmovgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmovfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmovgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmovfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movgs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_spr = -1; + in_GRj = FLD (in_GRj); + out_spr = FLD (out_spr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2spr (current_cpu, idesc, 0, referenced, in_GRj, out_spr); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movsg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movsg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_spr = -1; + INT out_GRj = -1; + in_spr = FLD (in_spr); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_spr2gr (current_cpu, idesc, 0, referenced, in_spr, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_beq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_blt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fblg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fblt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bctrlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_beqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_blelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_blslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bhilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bceqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bclelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bclslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bchilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_calll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_jmpil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_callil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_call (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_call.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_rett (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rett.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_rei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_teq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_thi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fteq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftlg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fto (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tils (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tihi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tic (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tinc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tin (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tip (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tinv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftilg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftio (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_break (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_break.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mtrap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_orcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xorcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nandcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_norcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_orncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nandncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_norncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_notcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ccklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ccknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ccknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cjmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ccalll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ici (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_icei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcef (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_witlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_wdtlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_itlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dtlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_icpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_icpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dcpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_icul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_icul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_dcul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_barrier (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_membar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_membar (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clrgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clrfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clrga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clrfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_commitgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_commitfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_commitga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_commitfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fitod (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fitod.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdtoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdtoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfitos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmovd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fnegd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fabsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fsqrtd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_faddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmuld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdivd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcmpd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcmpd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmaddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhsetlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRklo = FLD (out_FRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhsethis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRkhi = FLD (out_FRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhdsets (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdsets.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhsetloh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRklo = FLD (out_FRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhsethih (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethih.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRkhi = FLD (out_FRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhdseth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdseth.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mrotri (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mwcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mwcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_maveh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msrlhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_6 (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdrotli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcplhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcplhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msathu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcmpsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FCCk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FCCk = FLD (out_FCCk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcmpuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FCCk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FCCk = FLD (out_FCCk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mabshs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mabshs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_maddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_maddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintieven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintieven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_maddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_masaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdasaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmrdhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmrdhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Uk = FLD (out_ACC40Uk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 19)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Uk = FLD (out_ACC40Uk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 19)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqxmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_munpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_munpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdunpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRintj = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRintj = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_media_4_mclracca (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mrdacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mrdaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACCGi = -1; + INT in_FRinti = -1; + INT out_ACCGk = -1; + INT out_FRintk = -1; + in_ACCGi = FLD (in_ACCGi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mwtacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mwtaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACCGi = -1; + INT in_FRinti = -1; + INT out_ACCGk = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_ACCGk = FLD (out_ACCGk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_simple_add (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_addcc.f @@ -77269,102 +92967,6 @@ model_simple_stc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_simple_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_simple_std (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstdu.f @@ -77413,38 +93015,6 @@ model_simple_stdc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_simple_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_simple_stq (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_smulcc.f @@ -77493,38 +93063,6 @@ model_simple_stqc (SIM_CPU *current_cpu, void *sem_arg) } static int -model_simple_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_simple_stbu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_cstbu.f @@ -82949,6 +98487,54 @@ model_simple_membar (SIM_CPU *current_cpu, void *sem_arg) } static int +model_simple_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_simple_cop1 (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -85301,6 +100887,70 @@ model_simple_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) } static int +model_simple_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_simple_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_mdasaccs.f @@ -86561,22 +102211,12 @@ static const INSN_TIMING frv_timing[] = { { FRVBF_INSN_STHF, model_frv_sthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STF, model_frv_stf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STC, model_frv_stc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_frv_rstb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_frv_rsth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_frv_rst, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_frv_rstbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_frv_rsthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_frv_rstf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_frv_std, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDF, model_frv_stdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDC, model_frv_stdc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_frv_rstd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_frv_rstdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_frv_stq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_frv_stqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_frv_stqc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_frv_rstq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_frv_rstqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_frv_stbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STHU, model_frv_sthu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STU, model_frv_stu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, @@ -86916,6 +102556,9 @@ static const INSN_TIMING frv_timing[] = { { FRVBF_INSN_DCUL, model_frv_dcul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_BAR, model_frv_bar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_frv_membar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_frv_lrai, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_frv_lrad, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_frv_tlbpr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_frv_cop1, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_frv_cop2, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_frv_clrgr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, @@ -87063,6 +102706,10 @@ static const INSN_TIMING frv_timing[] = { { FRVBF_INSN_CMQADDHUS, model_frv_cmqaddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_frv_cmqsubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_frv_cmqsubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_frv_mqlclrhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_frv_mqlmths, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_frv_mqsllhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_frv_mqsrahi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_frv_maddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_frv_msubaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_frv_mdaddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, @@ -87318,22 +102965,12 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_STHF, model_fr550_sthf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STF, model_fr550_stf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STC, model_fr550_stc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_fr550_rstb, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_fr550_rsth, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_fr550_rst, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_fr550_rstbf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_fr550_rsthf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_fr550_rstf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_fr550_std, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STDF, model_fr550_stdf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STDC, model_fr550_stdc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_fr550_rstd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_fr550_rstdf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_fr550_stq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_fr550_stqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_fr550_stqc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_fr550_rstq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_fr550_rstqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_fr550_stbu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STHU, model_fr550_sthu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STU, model_fr550_stu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, @@ -87509,9 +103146,9 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_FCBULR, model_fr550_fcbulr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_FCBOLR, model_fr550_fcbolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_JMPL, model_fr550_jmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, - { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_JMPIL, model_fr550_jmpil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, - { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_CALL, model_fr550_call, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_RETT, model_fr550_rett, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_REI, model_fr550_rei, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, @@ -87656,7 +103293,7 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_CFCKU, model_fr550_cfcku, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, { FRVBF_INSN_CFCKO, model_fr550_cfcko, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, { FRVBF_INSN_CJMPL, model_fr550_cjmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, - { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_ICI, model_fr550_ici, { { (int) UNIT_FR550_U_ICI, 1, 1 } } }, { FRVBF_INSN_DCI, model_fr550_dci, { { (int) UNIT_FR550_U_DCI, 1, 1 } } }, { FRVBF_INSN_ICEI, model_fr550_icei, { { (int) UNIT_FR550_U_ICI, 1, 1 } } }, @@ -87673,6 +103310,9 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_DCUL, model_fr550_dcul, { { (int) UNIT_FR550_U_DCUL, 1, 1 } } }, { FRVBF_INSN_BAR, model_fr550_bar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_fr550_membar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_fr550_lrai, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_fr550_lrad, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_fr550_tlbpr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_fr550_cop1, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_fr550_cop2, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_fr550_clrgr, { { (int) UNIT_FR550_U_CLRGR, 1, 1 } } }, @@ -87820,6 +103460,10 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_CMQADDHUS, model_fr550_cmqaddhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_fr550_cmqsubhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_fr550_cmqsubhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_fr550_mqlclrhs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_fr550_mqlmths, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_fr550_mqsllhi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_fr550_mqsrahi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_fr550_maddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_fr550_msubaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_fr550_mdaddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC_DUAL, 1, 1 } } }, @@ -88075,22 +103719,12 @@ static const INSN_TIMING fr500_timing[] = { { FRVBF_INSN_STHF, model_fr500_sthf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STF, model_fr500_stf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STC, model_fr500_stc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_fr500_rstb, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_fr500_rsth, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RST, model_fr500_rst, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_fr500_rstbf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_fr500_rsthf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_fr500_rstf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, { FRVBF_INSN_STD, model_fr500_std, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STDF, model_fr500_stdf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STDC, model_fr500_stdc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_fr500_rstd, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_fr500_rstdf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, { FRVBF_INSN_STQ, model_fr500_stq, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STQF, model_fr500_stqf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STQC, model_fr500_stqc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_fr500_rstq, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_fr500_rstqf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, { FRVBF_INSN_STBU, model_fr500_stbu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STHU, model_fr500_sthu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STU, model_fr500_stu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, @@ -88430,6 +104064,9 @@ static const INSN_TIMING fr500_timing[] = { { FRVBF_INSN_DCUL, model_fr500_dcul, { { (int) UNIT_FR500_U_DCUL, 1, 1 } } }, { FRVBF_INSN_BAR, model_fr500_bar, { { (int) UNIT_FR500_U_BARRIER, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_fr500_membar, { { (int) UNIT_FR500_U_MEMBAR, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_fr500_lrai, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_fr500_lrad, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_fr500_tlbpr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_fr500_cop1, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_fr500_cop2, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_fr500_clrgr, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } }, @@ -88577,6 +104214,10 @@ static const INSN_TIMING fr500_timing[] = { { FRVBF_INSN_CMQADDHUS, model_fr500_cmqaddhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_fr500_cmqsubhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_fr500_cmqsubhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_fr500_mqlclrhs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_fr500_mqlmths, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_fr500_mqsllhi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_fr500_mqsrahi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_fr500_maddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_fr500_msubaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_fr500_mdaddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, @@ -88832,22 +104473,12 @@ static const INSN_TIMING tomcat_timing[] = { { FRVBF_INSN_STHF, model_tomcat_sthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STF, model_tomcat_stf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STC, model_tomcat_stc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_tomcat_rstb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_tomcat_rsth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_tomcat_rst, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_tomcat_rstbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_tomcat_rsthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_tomcat_rstf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_tomcat_std, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDF, model_tomcat_stdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDC, model_tomcat_stdc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_tomcat_rstd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_tomcat_rstdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_tomcat_stq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_tomcat_stqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_tomcat_stqc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_tomcat_rstq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_tomcat_rstqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_tomcat_stbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STHU, model_tomcat_sthu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STU, model_tomcat_stu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, @@ -89187,6 +104818,9 @@ static const INSN_TIMING tomcat_timing[] = { { FRVBF_INSN_DCUL, model_tomcat_dcul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_BAR, model_tomcat_bar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_tomcat_membar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_tomcat_lrai, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_tomcat_lrad, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_tomcat_tlbpr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_tomcat_cop1, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_tomcat_cop2, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_tomcat_clrgr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, @@ -89334,6 +104968,10 @@ static const INSN_TIMING tomcat_timing[] = { { FRVBF_INSN_CMQADDHUS, model_tomcat_cmqaddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_tomcat_cmqsubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_tomcat_cmqsubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_tomcat_mqlclrhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_tomcat_mqlmths, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_tomcat_mqsllhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_tomcat_mqsrahi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_tomcat_maddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_tomcat_msubaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_tomcat_mdaddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, @@ -89419,9 +105057,9 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_XOR, model_fr400_xor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_NOT, model_fr400_not, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_SDIV, model_fr400_sdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_UDIV, model_fr400_udiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_SMUL, model_fr400_smul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_UMUL, model_fr400_umul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_SMU, model_fr400_smu, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, @@ -89477,9 +105115,9 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_ORI, model_fr400_ori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_XORI, model_fr400_xori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_SDIVI, model_fr400_sdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_UDIVI, model_fr400_udivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_SMULI, model_fr400_smuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_UMULI, model_fr400_umuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_SLLI, model_fr400_slli, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, @@ -89589,22 +105227,12 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_STHF, model_fr400_sthf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STF, model_fr400_stf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STC, model_fr400_stc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_fr400_rstb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_fr400_rsth, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_fr400_rst, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_fr400_rstbf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_fr400_rsthf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_fr400_rstf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_fr400_std, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STDF, model_fr400_stdf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STDC, model_fr400_stdc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_fr400_rstd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_fr400_rstdf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_fr400_stq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_fr400_stqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_fr400_stqc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_fr400_rstq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_fr400_rstqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_fr400_stbu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STHU, model_fr400_sthu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STU, model_fr400_stu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, @@ -89944,6 +105572,9 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_DCUL, model_fr400_dcul, { { (int) UNIT_FR400_U_DCUL, 1, 1 } } }, { FRVBF_INSN_BAR, model_fr400_bar, { { (int) UNIT_FR400_U_BARRIER, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_fr400_membar, { { (int) UNIT_FR400_U_MEMBAR, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_fr400_lrai, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_fr400_lrad, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_fr400_tlbpr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_fr400_cop1, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_fr400_cop2, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_fr400_clrgr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, @@ -90091,6 +105722,10 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_CMQADDHUS, model_fr400_cmqaddhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_fr400_cmqsubhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_fr400_cmqsubhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_fr400_mqlclrhs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_fr400_mqlmths, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_fr400_mqsllhi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_fr400_mqsrahi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_fr400_maddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_fr400_msubaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_fr400_mdaddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC_DUAL, 1, 1 } } }, @@ -90160,6 +105795,760 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_FNOP, model_fr400_fnop, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, }; +/* Model timing data for `fr450'. */ + +static const INSN_TIMING fr450_timing[] = { + { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADD, model_fr450_add, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUB, model_fr450_sub, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_AND, model_fr450_and, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_OR, model_fr450_or, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XOR, model_fr450_xor, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_NOT, model_fr450_not, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIV, model_fr450_sdiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_fr450_nsdiv, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIV, model_fr450_udiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_fr450_nudiv, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMUL, model_fr450_smul, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMUL, model_fr450_umul, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SMU, model_fr450_smu, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMASS, model_fr450_smass, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMSSS, model_fr450_smsss, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLL, model_fr450_sll, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRL, model_fr450_srl, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRA, model_fr450_sra, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLASS, model_fr450_slass, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCUTSS, model_fr450_scutss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCAN, model_fr450_scan, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CADD, model_fr450_cadd, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUB, model_fr450_csub, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CAND, model_fr450_cand, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_COR, model_fr450_cor, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXOR, model_fr450_cxor, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CNOT, model_fr450_cnot, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMUL, model_fr450_csmul, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CSDIV, model_fr450_csdiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CUDIV, model_fr450_cudiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CSLL, model_fr450_csll, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRL, model_fr450_csrl, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRA, model_fr450_csra, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSCAN, model_fr450_cscan, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDCC, model_fr450_addcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBCC, model_fr450_subcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDCC, model_fr450_andcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORCC, model_fr450_orcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORCC, model_fr450_xorcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLLCC, model_fr450_sllcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLCC, model_fr450_srlcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRACC, model_fr450_sracc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULCC, model_fr450_smulcc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULCC, model_fr450_umulcc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CADDCC, model_fr450_caddcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUBCC, model_fr450_csubcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMULCC, model_fr450_csmulcc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CANDCC, model_fr450_candcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CORCC, model_fr450_corcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXORCC, model_fr450_cxorcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSLLCC, model_fr450_csllcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRLCC, model_fr450_csrlcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRACC, model_fr450_csracc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDX, model_fr450_addx, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBX, model_fr450_subx, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXCC, model_fr450_addxcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXCC, model_fr450_subxcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDSS, model_fr450_addss, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBSS, model_fr450_subss, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDI, model_fr450_addi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBI, model_fr450_subi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDI, model_fr450_andi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORI, model_fr450_ori, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORI, model_fr450_xori, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIVI, model_fr450_sdivi, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_fr450_nsdivi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIVI, model_fr450_udivi, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_fr450_nudivi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULI, model_fr450_smuli, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULI, model_fr450_umuli, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLI, model_fr450_slli, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLI, model_fr450_srli, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAI, model_fr450_srai, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SCANI, model_fr450_scani, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDICC, model_fr450_addicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBICC, model_fr450_subicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDICC, model_fr450_andicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORICC, model_fr450_oricc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORICC, model_fr450_xoricc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULICC, model_fr450_smulicc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULICC, model_fr450_umulicc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLICC, model_fr450_sllicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLICC, model_fr450_srlicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAICC, model_fr450_sraicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXI, model_fr450_addxi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXI, model_fr450_subxi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXICC, model_fr450_addxicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXICC, model_fr450_subxicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CMPB, model_fr450_cmpb, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CMPBA, model_fr450_cmpba, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SETLO, model_fr450_setlo, { { (int) UNIT_FR450_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETHI, model_fr450_sethi, { { (int) UNIT_FR450_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETLOS, model_fr450_setlos, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_LDSB, model_fr450_ldsb, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUB, model_fr450_ldub, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSH, model_fr450_ldsh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUH, model_fr450_lduh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LD, model_fr450_ld, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBF, model_fr450_ldbf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHF, model_fr450_ldhf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDF, model_fr450_ldf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDC, model_fr450_ldc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSB, model_fr450_nldsb, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUB, model_fr450_nldub, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSH, model_fr450_nldsh, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUH, model_fr450_nlduh, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLD, model_fr450_nld, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBF, model_fr450_nldbf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHF, model_fr450_nldhf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDF, model_fr450_nldf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDD, model_fr450_ldd, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDF, model_fr450_lddf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDC, model_fr450_lddc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDD, model_fr450_nldd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDF, model_fr450_nlddf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQ, model_fr450_ldq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQF, model_fr450_ldqf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQC, model_fr450_ldqc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQ, model_fr450_nldq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQF, model_fr450_nldqf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBU, model_fr450_ldsbu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBU, model_fr450_ldubu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHU, model_fr450_ldshu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHU, model_fr450_lduhu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDU, model_fr450_ldu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBU, model_fr450_nldsbu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBU, model_fr450_nldubu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHU, model_fr450_nldshu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHU, model_fr450_nlduhu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDU, model_fr450_nldu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBFU, model_fr450_ldbfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFU, model_fr450_ldhfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFU, model_fr450_ldfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDCU, model_fr450_ldcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFU, model_fr450_nldbfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFU, model_fr450_nldhfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFU, model_fr450_nldfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDU, model_fr450_lddu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDU, model_fr450_nlddu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDFU, model_fr450_lddfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDCU, model_fr450_lddcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFU, model_fr450_nlddfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQU, model_fr450_ldqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQU, model_fr450_nldqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFU, model_fr450_ldqfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQCU, model_fr450_ldqcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFU, model_fr450_nldqfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBI, model_fr450_ldsbi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHI, model_fr450_ldshi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDI, model_fr450_ldi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBI, model_fr450_ldubi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHI, model_fr450_lduhi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBFI, model_fr450_ldbfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFI, model_fr450_ldhfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFI, model_fr450_ldfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBI, model_fr450_nldsbi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBI, model_fr450_nldubi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHI, model_fr450_nldshi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHI, model_fr450_nlduhi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDI, model_fr450_nldi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFI, model_fr450_nldbfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFI, model_fr450_nldhfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFI, model_fr450_nldfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDI, model_fr450_lddi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDFI, model_fr450_lddfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDI, model_fr450_nlddi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFI, model_fr450_nlddfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQI, model_fr450_ldqi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFI, model_fr450_ldqfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFI, model_fr450_nldqfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STB, model_fr450_stb, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STH, model_fr450_sth, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_ST, model_fr450_st, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBF, model_fr450_stbf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHF, model_fr450_sthf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STF, model_fr450_stf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STC, model_fr450_stc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STD, model_fr450_std, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDF, model_fr450_stdf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDC, model_fr450_stdc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQ, model_fr450_stq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQF, model_fr450_stqf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQC, model_fr450_stqc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBU, model_fr450_stbu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHU, model_fr450_sthu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STU, model_fr450_stu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFU, model_fr450_stbfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFU, model_fr450_sthfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFU, model_fr450_stfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STCU, model_fr450_stcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDU, model_fr450_stdu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFU, model_fr450_stdfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDCU, model_fr450_stdcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQU, model_fr450_stqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFU, model_fr450_stqfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQCU, model_fr450_stqcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSB, model_fr450_cldsb, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUB, model_fr450_cldub, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSH, model_fr450_cldsh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUH, model_fr450_clduh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLD, model_fr450_cld, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBF, model_fr450_cldbf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHF, model_fr450_cldhf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDF, model_fr450_cldf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDD, model_fr450_cldd, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDF, model_fr450_clddf, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQ, model_fr450_cldq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSBU, model_fr450_cldsbu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUBU, model_fr450_cldubu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSHU, model_fr450_cldshu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUHU, model_fr450_clduhu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDU, model_fr450_cldu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBFU, model_fr450_cldbfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHFU, model_fr450_cldhfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDFU, model_fr450_cldfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDU, model_fr450_clddu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDFU, model_fr450_clddfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQU, model_fr450_cldqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTB, model_fr450_cstb, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTH, model_fr450_csth, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CST, model_fr450_cst, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBF, model_fr450_cstbf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHF, model_fr450_csthf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTF, model_fr450_cstf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTD, model_fr450_cstd, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDF, model_fr450_cstdf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTQ, model_fr450_cstq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBU, model_fr450_cstbu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHU, model_fr450_csthu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTU, model_fr450_cstu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBFU, model_fr450_cstbfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHFU, model_fr450_csthfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTFU, model_fr450_cstfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDU, model_fr450_cstdu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDFU, model_fr450_cstdfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBI, model_fr450_stbi, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHI, model_fr450_sthi, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STI, model_fr450_sti, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFI, model_fr450_stbfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFI, model_fr450_sthfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFI, model_fr450_stfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDI, model_fr450_stdi, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFI, model_fr450_stdfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQI, model_fr450_stqi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFI, model_fr450_stqfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAP, model_fr450_swap, { { (int) UNIT_FR450_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_SWAPI, model_fr450_swapi, { { (int) UNIT_FR450_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_CSWAP, model_fr450_cswap, { { (int) UNIT_FR450_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_MOVGF, model_fr450_movgf, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFG, model_fr450_movfg, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFD, model_fr450_movgfd, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFGD, model_fr450_movfgd, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFQ, model_fr450_movgfq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGQ, model_fr450_movfgq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGF, model_fr450_cmovgf, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFG, model_fr450_cmovfg, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_CMOVGFD, model_fr450_cmovgfd, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFGD, model_fr450_cmovfgd, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGS, model_fr450_movgs, { { (int) UNIT_FR450_U_GR2SPR, 1, 1 } } }, + { FRVBF_INSN_MOVSG, model_fr450_movsg, { { (int) UNIT_FR450_U_SPR2GR, 1, 1 } } }, + { FRVBF_INSN_BRA, model_fr450_bra, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNO, model_fr450_bno, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQ, model_fr450_beq, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNE, model_fr450_bne, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLE, model_fr450_ble, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGT, model_fr450_bgt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLT, model_fr450_blt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGE, model_fr450_bge, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLS, model_fr450_bls, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHI, model_fr450_bhi, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BC, model_fr450_bc, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNC, model_fr450_bnc, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BN, model_fr450_bn, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BP, model_fr450_bp, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BV, model_fr450_bv, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNV, model_fr450_bnv, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRA, model_fr450_fbra, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNO, model_fr450_fbno, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNE, model_fr450_fbne, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQ, model_fr450_fbeq, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLG, model_fr450_fblg, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUE, model_fr450_fbue, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUL, model_fr450_fbul, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGE, model_fr450_fbge, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLT, model_fr450_fblt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGE, model_fr450_fbuge, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUG, model_fr450_fbug, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLE, model_fr450_fble, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGT, model_fr450_fbgt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULE, model_fr450_fbule, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBU, model_fr450_fbu, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBO, model_fr450_fbo, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCTRLR, model_fr450_bctrlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BRALR, model_fr450_bralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNOLR, model_fr450_bnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQLR, model_fr450_beqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNELR, model_fr450_bnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLELR, model_fr450_blelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGTLR, model_fr450_bgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLTLR, model_fr450_bltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGELR, model_fr450_bgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLSLR, model_fr450_blslr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHILR, model_fr450_bhilr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLR, model_fr450_bclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNCLR, model_fr450_bnclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNLR, model_fr450_bnlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BPLR, model_fr450_bplr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BVLR, model_fr450_bvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNVLR, model_fr450_bnvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRALR, model_fr450_fbralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNOLR, model_fr450_fbnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQLR, model_fr450_fbeqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNELR, model_fr450_fbnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLGLR, model_fr450_fblglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUELR, model_fr450_fbuelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULLR, model_fr450_fbullr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGELR, model_fr450_fbgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLTLR, model_fr450_fbltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGELR, model_fr450_fbugelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGLR, model_fr450_fbuglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLELR, model_fr450_fblelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGTLR, model_fr450_fbgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULELR, model_fr450_fbulelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULR, model_fr450_fbulr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBOLR, model_fr450_fbolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCRALR, model_fr450_bcralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNOLR, model_fr450_bcnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCEQLR, model_fr450_bceqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNELR, model_fr450_bcnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLELR, model_fr450_bclelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGTLR, model_fr450_bcgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLTLR, model_fr450_bcltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGELR, model_fr450_bcgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLSLR, model_fr450_bclslr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCHILR, model_fr450_bchilr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCCLR, model_fr450_bcclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNCLR, model_fr450_bcnclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNLR, model_fr450_bcnlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCPLR, model_fr450_bcplr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCVLR, model_fr450_bcvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNVLR, model_fr450_bcnvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBRALR, model_fr450_fcbralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNOLR, model_fr450_fcbnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBEQLR, model_fr450_fcbeqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNELR, model_fr450_fcbnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLGLR, model_fr450_fcblglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUELR, model_fr450_fcbuelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULLR, model_fr450_fcbullr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGELR, model_fr450_fcbgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLTLR, model_fr450_fcbltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGELR, model_fr450_fcbugelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGLR, model_fr450_fcbuglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLELR, model_fr450_fcblelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGTLR, model_fr450_fcbgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULELR, model_fr450_fcbulelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULR, model_fr450_fcbulr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBOLR, model_fr450_fcbolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_JMPL, model_fr450_jmpl, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_fr450_calll, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_JMPIL, model_fr450_jmpil, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_fr450_callil, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALL, model_fr450_call, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_RETT, model_fr450_rett, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_REI, model_fr450_rei, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TRA, model_fr450_tra, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNO, model_fr450_tno, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TEQ, model_fr450_teq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNE, model_fr450_tne, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLE, model_fr450_tle, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGT, model_fr450_tgt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLT, model_fr450_tlt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGE, model_fr450_tge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLS, model_fr450_tls, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_THI, model_fr450_thi, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TC, model_fr450_tc, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNC, model_fr450_tnc, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TN, model_fr450_tn, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TP, model_fr450_tp, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TV, model_fr450_tv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNV, model_fr450_tnv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTRA, model_fr450_ftra, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNO, model_fr450_ftno, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNE, model_fr450_ftne, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTEQ, model_fr450_fteq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLG, model_fr450_ftlg, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUE, model_fr450_ftue, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUL, model_fr450_ftul, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGE, model_fr450_ftge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLT, model_fr450_ftlt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUGE, model_fr450_ftuge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUG, model_fr450_ftug, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLE, model_fr450_ftle, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGT, model_fr450_ftgt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTULE, model_fr450_ftule, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTU, model_fr450_ftu, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTO, model_fr450_fto, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIRA, model_fr450_tira, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINO, model_fr450_tino, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIEQ, model_fr450_tieq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINE, model_fr450_tine, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILE, model_fr450_tile, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGT, model_fr450_tigt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILT, model_fr450_tilt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGE, model_fr450_tige, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILS, model_fr450_tils, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIHI, model_fr450_tihi, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIC, model_fr450_tic, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINC, model_fr450_tinc, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIN, model_fr450_tin, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIP, model_fr450_tip, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIV, model_fr450_tiv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINV, model_fr450_tinv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIRA, model_fr450_ftira, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTINO, model_fr450_ftino, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTINE, model_fr450_ftine, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIEQ, model_fr450_ftieq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILG, model_fr450_ftilg, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUE, model_fr450_ftiue, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUL, model_fr450_ftiul, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGE, model_fr450_ftige, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILT, model_fr450_ftilt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUGE, model_fr450_ftiuge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUG, model_fr450_ftiug, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILE, model_fr450_ftile, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGT, model_fr450_ftigt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIULE, model_fr450_ftiule, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIU, model_fr450_ftiu, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIO, model_fr450_ftio, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_BREAK, model_fr450_break, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MTRAP, model_fr450_mtrap, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCR, model_fr450_andcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCR, model_fr450_orcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCR, model_fr450_xorcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDCR, model_fr450_nandcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORCR, model_fr450_norcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDNCR, model_fr450_andncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORNCR, model_fr450_orncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDNCR, model_fr450_nandncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORNCR, model_fr450_norncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOTCR, model_fr450_notcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKRA, model_fr450_ckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNO, model_fr450_ckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKEQ, model_fr450_ckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNE, model_fr450_ckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLE, model_fr450_ckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGT, model_fr450_ckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLT, model_fr450_cklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGE, model_fr450_ckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLS, model_fr450_ckls, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKHI, model_fr450_ckhi, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKC, model_fr450_ckc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNC, model_fr450_cknc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKN, model_fr450_ckn, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKP, model_fr450_ckp, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKV, model_fr450_ckv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNV, model_fr450_cknv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKRA, model_fr450_fckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNO, model_fr450_fckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNE, model_fr450_fckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKEQ, model_fr450_fckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLG, model_fr450_fcklg, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUE, model_fr450_fckue, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUL, model_fr450_fckul, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGE, model_fr450_fckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLT, model_fr450_fcklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUGE, model_fr450_fckuge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUG, model_fr450_fckug, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLE, model_fr450_fckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGT, model_fr450_fckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKULE, model_fr450_fckule, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKU, model_fr450_fcku, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKO, model_fr450_fcko, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKRA, model_fr450_cckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNO, model_fr450_cckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKEQ, model_fr450_cckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNE, model_fr450_cckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLE, model_fr450_cckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGT, model_fr450_cckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLT, model_fr450_ccklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGE, model_fr450_cckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLS, model_fr450_cckls, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKHI, model_fr450_cckhi, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKC, model_fr450_cckc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNC, model_fr450_ccknc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKN, model_fr450_cckn, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKP, model_fr450_cckp, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKV, model_fr450_cckv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNV, model_fr450_ccknv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKRA, model_fr450_cfckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNO, model_fr450_cfckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNE, model_fr450_cfckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKEQ, model_fr450_cfckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLG, model_fr450_cfcklg, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUE, model_fr450_cfckue, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUL, model_fr450_cfckul, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGE, model_fr450_cfckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLT, model_fr450_cfcklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUGE, model_fr450_cfckuge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUG, model_fr450_cfckug, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLE, model_fr450_cfckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGT, model_fr450_cfckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKULE, model_fr450_cfckule, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKU, model_fr450_cfcku, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKO, model_fr450_cfcko, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CJMPL, model_fr450_cjmpl, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_fr450_ccalll, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_ICI, model_fr450_ici, { { (int) UNIT_FR450_U_ICI, 1, 1 } } }, + { FRVBF_INSN_DCI, model_fr450_dci, { { (int) UNIT_FR450_U_DCI, 1, 1 } } }, + { FRVBF_INSN_ICEI, model_fr450_icei, { { (int) UNIT_FR450_U_ICI, 1, 1 } } }, + { FRVBF_INSN_DCEI, model_fr450_dcei, { { (int) UNIT_FR450_U_DCI, 1, 1 } } }, + { FRVBF_INSN_DCF, model_fr450_dcf, { { (int) UNIT_FR450_U_DCF, 1, 1 } } }, + { FRVBF_INSN_DCEF, model_fr450_dcef, { { (int) UNIT_FR450_U_DCF, 1, 1 } } }, + { FRVBF_INSN_WITLB, model_fr450_witlb, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WDTLB, model_fr450_wdtlb, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ITLBI, model_fr450_itlbi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DTLBI, model_fr450_dtlbi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICPL, model_fr450_icpl, { { (int) UNIT_FR450_U_ICPL, 1, 1 } } }, + { FRVBF_INSN_DCPL, model_fr450_dcpl, { { (int) UNIT_FR450_U_DCPL, 1, 1 } } }, + { FRVBF_INSN_ICUL, model_fr450_icul, { { (int) UNIT_FR450_U_ICUL, 1, 1 } } }, + { FRVBF_INSN_DCUL, model_fr450_dcul, { { (int) UNIT_FR450_U_DCUL, 1, 1 } } }, + { FRVBF_INSN_BAR, model_fr450_bar, { { (int) UNIT_FR450_U_BARRIER, 1, 1 } } }, + { FRVBF_INSN_MEMBAR, model_fr450_membar, { { (int) UNIT_FR450_U_MEMBAR, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_fr450_lrai, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_fr450_lrad, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_fr450_tlbpr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP1, model_fr450_cop1, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP2, model_fr450_cop2, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGR, model_fr450_clrgr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFR, model_fr450_clrfr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGA, model_fr450_clrga, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFA, model_fr450_clrfa, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGR, model_fr450_commitgr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFR, model_fr450_commitfr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGA, model_fr450_commitga, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFA, model_fr450_commitfa, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOS, model_fr450_fitos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSTOI, model_fr450_fstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOD, model_fr450_fitod, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDTOI, model_fr450_fdtoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDITOS, model_fr450_fditos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSTOI, model_fr450_fdstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDITOS, model_fr450_nfditos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSTOI, model_fr450_nfdstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFITOS, model_fr450_cfitos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSTOI, model_fr450_cfstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFITOS, model_fr450_nfitos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSTOI, model_fr450_nfstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVS, model_fr450_fmovs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVD, model_fr450_fmovd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMOVS, model_fr450_fdmovs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMOVS, model_fr450_cfmovs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGS, model_fr450_fnegs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGD, model_fr450_fnegd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDNEGS, model_fr450_fdnegs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFNEGS, model_fr450_cfnegs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSS, model_fr450_fabss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSD, model_fr450_fabsd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDABSS, model_fr450_fdabss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFABSS, model_fr450_cfabss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTS, model_fr450_fsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSQRTS, model_fr450_fdsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSQRTS, model_fr450_nfdsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTD, model_fr450_fsqrtd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSQRTS, model_fr450_cfsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSQRTS, model_fr450_nfsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDS, model_fr450_fadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBS, model_fr450_fsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULS, model_fr450_fmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVS, model_fr450_fdivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDD, model_fr450_faddd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBD, model_fr450_fsubd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULD, model_fr450_fmuld, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVD, model_fr450_fdivd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFADDS, model_fr450_cfadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSUBS, model_fr450_cfsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMULS, model_fr450_cfmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFDIVS, model_fr450_cfdivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFADDS, model_fr450_nfadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSUBS, model_fr450_nfsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMULS, model_fr450_nfmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDIVS, model_fr450_nfdivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPS, model_fr450_fcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPD, model_fr450_fcmpd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCMPS, model_fr450_cfcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDCMPS, model_fr450_fdcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDS, model_fr450_fmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBS, model_fr450_fmsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDD, model_fr450_fmaddd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBD, model_fr450_fmsubd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMADDS, model_fr450_fdmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMADDS, model_fr450_nfdmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMADDS, model_fr450_cfmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSUBS, model_fr450_cfmsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMADDS, model_fr450_nfmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSUBS, model_fr450_nfmsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAS, model_fr450_fmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSS, model_fr450_fmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMAS, model_fr450_fdmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMSS, model_fr450_fdmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMAS, model_fr450_nfdmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMSS, model_fr450_nfdmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMAS, model_fr450_cfmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSS, model_fr450_cfmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAD, model_fr450_fmad, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSD, model_fr450_fmsd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMAS, model_fr450_nfmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSS, model_fr450_nfmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDADDS, model_fr450_fdadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSUBS, model_fr450_fdsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULS, model_fr450_fdmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDDIVS, model_fr450_fddivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSADS, model_fr450_fdsads, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULCS, model_fr450_fdmulcs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULCS, model_fr450_nfdmulcs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDADDS, model_fr450_nfdadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSUBS, model_fr450_nfdsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULS, model_fr450_nfdmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDDIVS, model_fr450_nfddivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSADS, model_fr450_nfdsads, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDCMPS, model_fr450_nfdcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOS, model_fr450_mhsetlos, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHSETHIS, model_fr450_mhsethis, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHDSETS, model_fr450_mhdsets, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MHSETLOH, model_fr450_mhsetloh, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHSETHIH, model_fr450_mhsethih, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHDSETH, model_fr450_mhdseth, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MAND, model_fr450_mand, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MOR, model_fr450_mor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MXOR, model_fr450_mxor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMAND, model_fr450_cmand, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMOR, model_fr450_cmor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMXOR, model_fr450_cmxor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MNOT, model_fr450_mnot, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMNOT, model_fr450_cmnot, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MROTLI, model_fr450_mrotli, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MROTRI, model_fr450_mrotri, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MWCUT, model_fr450_mwcut, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MWCUTI, model_fr450_mwcuti, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MCUT, model_fr450_mcut, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCUTI, model_fr450_mcuti, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCUTSS, model_fr450_mcutss, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCUTSSI, model_fr450_mcutssi, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MDCUTSSI, model_fr450_mdcutssi, { { (int) UNIT_FR450_U_MEDIA_4_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MAVEH, model_fr450_maveh, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MSLLHI, model_fr450_msllhi, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MSRLHI, model_fr450_msrlhi, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MSRAHI, model_fr450_msrahi, { { (int) UNIT_FR450_U_MEDIA_6, 1, 1 } } }, + { FRVBF_INSN_MDROTLI, model_fr450_mdrotli, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MCPLHI, model_fr450_mcplhi, { { (int) UNIT_FR450_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_MCPLI, model_fr450_mcpli, { { (int) UNIT_FR450_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_MSATHS, model_fr450_msaths, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MQSATHS, model_fr450_mqsaths, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MSATHU, model_fr450_msathu, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MCMPSH, model_fr450_mcmpsh, { { (int) UNIT_FR450_U_MEDIA_7, 1, 1 } } }, + { FRVBF_INSN_MCMPUH, model_fr450_mcmpuh, { { (int) UNIT_FR450_U_MEDIA_7, 1, 1 } } }, + { FRVBF_INSN_MABSHS, model_fr450_mabshs, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MADDHSS, model_fr450_maddhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MADDHUS, model_fr450_maddhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MSUBHSS, model_fr450_msubhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MSUBHUS, model_fr450_msubhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMADDHSS, model_fr450_cmaddhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMADDHUS, model_fr450_cmaddhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMSUBHSS, model_fr450_cmsubhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMSUBHUS, model_fr450_cmsubhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MQADDHSS, model_fr450_mqaddhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQADDHUS, model_fr450_mqaddhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSUBHSS, model_fr450_mqsubhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSUBHUS, model_fr450_mqsubhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQADDHSS, model_fr450_cmqaddhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQADDHUS, model_fr450_cmqaddhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHSS, model_fr450_cmqsubhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHUS, model_fr450_cmqsubhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_fr450_mqlclrhs, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_fr450_mqlmths, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_fr450_mqsllhi, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_fr450_mqsrahi, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MADDACCS, model_fr450_maddaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC, 1, 1 } } }, + { FRVBF_INSN_MSUBACCS, model_fr450_msubaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC, 1, 1 } } }, + { FRVBF_INSN_MDADDACCS, model_fr450_mdaddaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MDSUBACCS, model_fr450_mdsubaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MASACCS, model_fr450_masaccs, { { (int) UNIT_FR450_U_MEDIA_2_ADD_SUB, 1, 1 } } }, + { FRVBF_INSN_MDASACCS, model_fr450_mdasaccs, { { (int) UNIT_FR450_U_MEDIA_2_ADD_SUB_DUAL, 1, 1 } } }, + { FRVBF_INSN_MMULHS, model_fr450_mmulhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMULHU, model_fr450_mmulhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMULXHS, model_fr450_mmulxhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMULXHU, model_fr450_mmulxhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMULHS, model_fr450_cmmulhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMULHU, model_fr450_cmmulhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MQMULHS, model_fr450_mqmulhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULHU, model_fr450_mqmulhu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULXHS, model_fr450_mqmulxhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULXHU, model_fr450_mqmulxhu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMULHS, model_fr450_cmqmulhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMULHU, model_fr450_cmqmulhu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MMACHS, model_fr450_mmachs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMACHU, model_fr450_mmachu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMRDHS, model_fr450_mmrdhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMRDHU, model_fr450_mmrdhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMACHS, model_fr450_cmmachs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMACHU, model_fr450_cmmachu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MQMACHS, model_fr450_mqmachs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMACHU, model_fr450_mqmachu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMACHS, model_fr450_cmqmachs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMACHU, model_fr450_cmqmachu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQXMACHS, model_fr450_mqxmachs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQXMACXHS, model_fr450_mqxmacxhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMACXHS, model_fr450_mqmacxhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MCPXRS, model_fr450_mcpxrs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MCPXRU, model_fr450_mcpxru, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MCPXIS, model_fr450_mcpxis, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MCPXIU, model_fr450_mcpxiu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXRS, model_fr450_cmcpxrs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXRU, model_fr450_cmcpxru, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXIS, model_fr450_cmcpxis, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXIU, model_fr450_cmcpxiu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MQCPXRS, model_fr450_mqcpxrs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXRU, model_fr450_mqcpxru, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXIS, model_fr450_mqcpxis, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXIU, model_fr450_mqcpxiu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MEXPDHW, model_fr450_mexpdhw, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHW, model_fr450_cmexpdhw, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MEXPDHD, model_fr450_mexpdhd, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHD, model_fr450_cmexpdhd, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MPACKH, model_fr450_mpackh, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MDPACKH, model_fr450_mdpackh, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MUNPACKH, model_fr450_munpackh, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MDUNPACKH, model_fr450_mdunpackh, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOH, model_fr450_mbtoh, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_CMBTOH, model_fr450_cmbtoh, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MHTOB, model_fr450_mhtob, { { (int) UNIT_FR450_U_MEDIA_DUAL_HTOB, 1, 1 } } }, + { FRVBF_INSN_CMHTOB, model_fr450_cmhtob, { { (int) UNIT_FR450_U_MEDIA_DUAL_HTOB, 1, 1 } } }, + { FRVBF_INSN_MBTOHE, model_fr450_mbtohe, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOHE, model_fr450_cmbtohe, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOP, model_fr450_mnop, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_0, model_fr450_mclracc_0, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_1, model_fr450_mclracc_1, { { (int) UNIT_FR450_U_MEDIA_4_MCLRACCA, 1, 1 } } }, + { FRVBF_INSN_MRDACC, model_fr450_mrdacc, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MRDACCG, model_fr450_mrdaccg, { { (int) UNIT_FR450_U_MEDIA_4_ACCG, 1, 1 } } }, + { FRVBF_INSN_MWTACC, model_fr450_mwtacc, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MWTACCG, model_fr450_mwtaccg, { { (int) UNIT_FR450_U_MEDIA_4_ACCG, 1, 1 } } }, + { FRVBF_INSN_MCOP1, model_fr450_mcop1, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP2, model_fr450_mcop2, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNOP, model_fr450_fnop, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, +}; + /* Model timing data for `simple'. */ static const INSN_TIMING simple_timing[] = { @@ -90346,22 +106735,12 @@ static const INSN_TIMING simple_timing[] = { { FRVBF_INSN_STHF, model_simple_sthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STF, model_simple_stf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STC, model_simple_stc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_simple_rstb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_simple_rsth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_simple_rst, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_simple_rstbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_simple_rsthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_simple_rstf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_simple_std, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDF, model_simple_stdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDC, model_simple_stdc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_simple_rstd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_simple_rstdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_simple_stq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_simple_stqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_simple_stqc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_simple_rstq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_simple_rstqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_simple_stbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STHU, model_simple_sthu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STU, model_simple_stu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, @@ -90701,6 +107080,9 @@ static const INSN_TIMING simple_timing[] = { { FRVBF_INSN_DCUL, model_simple_dcul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_BAR, model_simple_bar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_simple_membar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_simple_lrai, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_simple_lrad, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_simple_tlbpr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_simple_cop1, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_simple_cop2, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_simple_clrgr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, @@ -90848,6 +107230,10 @@ static const INSN_TIMING simple_timing[] = { { FRVBF_INSN_CMQADDHUS, model_simple_cmqaddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_simple_cmqsubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_simple_cmqsubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_simple_mqlclrhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_simple_mqlmths, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_simple_mqsllhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_simple_mqsrahi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_simple_maddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_simple_msubaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_simple_mdaddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, @@ -90950,6 +107336,12 @@ fr400_model_init (SIM_CPU *cpu) } static void +fr450_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR450_DATA)); +} + +static void simple_model_init (SIM_CPU *cpu) { CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_SIMPLE_DATA)); @@ -90991,6 +107383,12 @@ static const MODEL fr400_models[] = { 0 } }; +static const MODEL fr450_models[] = +{ + { "fr450", & fr450_mach, MODEL_FR450, TIMING_DATA (& fr450_timing[0]), fr450_model_init }, + { 0 } +}; + static const MODEL simple_models[] = { { "simple", & simple_mach, MODEL_SIMPLE, TIMING_DATA (& simple_timing[0]), simple_model_init }, @@ -91154,6 +107552,32 @@ const MACH fr400_mach = }; static void +fr450_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = frvbf_fetch_register; + CPU_REG_STORE (cpu) = frvbf_store_register; + CPU_PC_FETCH (cpu) = frvbf_h_pc_get; + CPU_PC_STORE (cpu) = frvbf_h_pc_set; + CPU_GET_IDATA (cpu) = frvbf_get_idata; + CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full; +#endif +} + +const MACH fr450_mach = +{ + "fr450", "fr450", MACH_FR450, + 32, 32, & fr450_models[0], & frvbf_imp_properties, + fr450_init_cpu, + frvbf_prepare_run +}; + +static void simple_init_cpu (SIM_CPU *cpu) { CPU_REG_FETCH (cpu) = frvbf_fetch_register; diff --git a/sim/frv/profile-fr450.c b/sim/frv/profile-fr450.c new file mode 100644 index 0000000..27b9755 --- /dev/null +++ b/sim/frv/profile-fr450.c @@ -0,0 +1,607 @@ +/* frv simulator fr450 dependent profiling code. + + Copyright (C) 2001, 2004 Free Software Foundation, Inc. + Contributed by Red Hat + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ +#define WANT_CPU +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "bfd.h" + +#if WITH_PROFILE_MODEL_P + +#include "profile.h" +#include "profile-fr400.h" + +int +frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + return idesc->timing->units[unit_num].done; +} + +int +frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, + INT out_ICCi_1) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, out_ICCi_1); +} + +int +frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr500. */ + return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + /* GRk and IACCi_1 have a latency of 1 cycle. */ + cycles = idesc->timing->units[unit_num].done; + update_GRdouble_latency (cpu, out_GRk, cycles + 1); + update_CCR_latency (cpu, out_ICCi_1, cycles + 1); + + return cycles; +} + +int +frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr500. */ + return frvbf_model_fr500_u_idiv (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + /* GRk, ICCi_1 and the divider have a latency of 18 cycles */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRk, cycles + 18); + update_CCR_latency (cpu, out_ICCi_1, cycles + 18); + update_idiv_resource_latency (cpu, 0, cycles + 18); + + return cycles; +} + +int +frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_ICCi_3) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_branch (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_ICCi_2, in_ICCi_3); +} + +int +frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_FCCi_2) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); +} + +int +frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ICCi_3, INT in_FCCi_3) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, + in_ICCi_3, in_FCCi_3); +} + +int +frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT out_GRkhi, INT out_GRklo) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced, + out_GRkhi, out_GRklo); +} + +int +frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_GRk, INT out_GRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr500. */ + return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, + out_GRdoublek); + } + + cycles = idesc->timing->units[unit_num].done; + + /* The latency of GRk for a load will depend on how long it takes to retrieve + the the data from the cache or memory. */ + update_GR_latency_for_load (cpu, out_GRk, cycles); + update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* GNER has a latency of 2 cycles. */ + update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2); + update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2); + } + + return cycles; +} + +int +frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_GRk, INT in_GRdoublek) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_GRk, in_GRdoublek); +} + +int +frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_FRk, INT out_FRdoublek) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_FRk, out_FRdoublek); +} + +int +frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_FRk, INT in_FRdoublek) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_FRk, in_FRdoublek); +} + +int +frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk); +} + +int +frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRk, INT out_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr400. */ + return frvbf_model_fr500_u_fr2gr (cpu, idesc, unit_num, referenced, + in_FRk, out_GRj); + } + + /* The latency of GRj is 1 cycle. */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRj, cycles + 1); + + return cycles; +} + +int +frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_spr, INT out_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, + in_spr, out_GRj); +} + +int +frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_gr2fr (cpu, idesc, unit_num, referenced, + in_GRj, out_FRk); +} + +int +frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_spr) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced, + in_GRj, out_spr); +} + +int +frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT out_FRkhi, INT out_FRklo) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_hilo (cpu, idesc, unit_num, referenced, + out_FRkhi, out_FRklo); +} + +int +frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_ACC40Sk, + out_ACC40Uk); +} + +int +frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_ACC40Sk, + out_ACC40Uk); +} + +int +frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced, + in_ACC40Si, out_ACC40Sk); +} + +int +frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num, + referenced, in_ACC40Si, + out_ACC40Sk); +} + +int +frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num, + referenced, in_ACC40Si, + out_ACC40Sk); +} + +int +frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num, + referenced, in_ACC40Si, + out_ACC40Sk); +} + +int +frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling is the same as media unit 1. */ + return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced, + in_FRi, out_FRk); +} + +int +frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling is the same as media unit 1. */ + return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT in_FRj, + INT out_ACC40Sk, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced, + in_ACC40Si, in_FRj, + out_ACC40Sk, out_FRk); +} + +int +frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACCGi, INT in_FRinti, + INT out_ACCGk, INT out_FRintk) +{ + /* Modelling is the same as media-4 unit except use accumulator guards + as input instead of accumulators. */ + return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced, + in_ACCGi, in_FRinti, + out_ACCGk, out_FRintk); +} + +int +frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num, + referenced, in_ACC40Si, + out_FRk); +} + +int +frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + int cycles; + int acc; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + + /* The post processing must wait for any pending ACC writes. */ + ps->post_wait = cycles; + for (acc = 0; acc < 4; acc++) + post_wait_for_ACC (cpu, acc); + for (acc = 8; acc < 12; acc++) + post_wait_for_ACC (cpu, acc); + + for (acc = 0; acc < 4; acc++) + { + update_ACC_latency (cpu, acc, ps->post_wait); + update_ACC_ptime (cpu, acc, 2); + } + for (acc = 8; acc < 12; acc++) + { + update_ACC_latency (cpu, acc, ps->post_wait); + update_ACC_ptime (cpu, acc, 2); + } + + return cycles; +} + +int +frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced, + in_FRi, out_FRk); +} + +int +frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRinti, INT in_FRintj, + INT out_FCCk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced, + in_FRinti, in_FRintj, out_FCCk); +} + +int +frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, + INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num, + referenced, in_FRi, out_FRk); +} + +int +frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, + INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num, + referenced, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced); +} + +int +frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced); +} + +#endif /* WITH_PROFILE_MODEL_P */ diff --git a/sim/frv/profile.c b/sim/frv/profile.c index 3a3d1aa..577826f 100644 --- a/sim/frv/profile.c +++ b/sim/frv/profile.c @@ -37,7 +37,8 @@ static void reset_gr_flags (SIM_CPU *cpu, INT gr) { SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 + || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) fr400_reset_gr_flags (cpu, gr); /* Other machines have no gr flags right now. */ } @@ -46,7 +47,8 @@ static void reset_fr_flags (SIM_CPU *cpu, INT fr) { SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 + || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) fr400_reset_fr_flags (cpu, fr); else if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) fr500_reset_fr_flags (cpu, fr); @@ -56,7 +58,8 @@ static void reset_acc_flags (SIM_CPU *cpu, INT acc) { SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 + || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) fr400_reset_acc_flags (cpu, acc); /* Other machines have no acc flags right now. */ } @@ -926,6 +929,7 @@ frvbf_model_insn_before (SIM_CPU *cpu, int first_p) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: fr400_model_insn_before (cpu, first_p); break; case bfd_mach_fr500: @@ -992,6 +996,7 @@ frvbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: fr400_model_insn_after (cpu, last_p, cycles); break; case bfd_mach_fr500: diff --git a/sim/frv/registers.c b/sim/frv/registers.c index 685e53f..aa65bb2 100644 --- a/sim/frv/registers.c +++ b/sim/frv/registers.c @@ -5301,6 +5301,1047 @@ static FRV_SPR_CONTROL_INFO fr400_spr[] = RESERVED }; +/* SPR definitions for the fr450 machine. + See the FR451 LSI for implementation details. */ +static FRV_SPR_CONTROL_INFO fr450_spr[] = +{ + {0x200030fe, 0x200030fc, 0xf00030fd, 0xffffff80, IMPL, SUP}, /* PSR */ + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */ + {0x00000000, 0x00000000, 0x0000000f, 0x00000fff, IMPL, SUP}, /* TBR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffeffe, IMPL, SUP}, /* BPSR */ + + /* spr registers 5-15 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000d40, 0x00000d40, 0xcc400fc0, 0x20742ff8, IMPL, SUP}, /* HSR0 */ + + /* spr registers 17-255 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* CCR */ + + /* spr registers 257-262 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffff0000, IMPL, USER}, /* CCCR */ + + /* spr registers 264-271 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */ + + /* spr registers 274-279 and reserved. */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */ + + /* spr registers 282-287 and reserved. */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */ + + /* spr registers 289-511 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */ + + /* spr registers 513-575 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */ + + /* spr registers 577-589 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR14 */ + {0x00000800, 0x00000800, 0x00000800, 0xffffffff, IMPL, SUP}, + + /* spr registers 592-672 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */ + + /* spr registers 674-831 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* SCR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, + + /* spr registers 836-1279 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x01c00000, 0x0fff8fc0, IMPL, USER}, /* MSR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffcd, IMPL, USER}, + + /* spr registers 1282-1407 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + /* Accumulators are read-only by the user except for special insns and + side effect of other insns. ACC0-3 (1408-1411) and ACC8-11 (1416-1419) + are implemented, ACC4-7 are not. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC8 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + /* spr registers 1420-1471 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* Accumulator guards (1472-1483). See comments above ACC0. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG8 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + /* spr registers 1484-1535 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR0 */ + + /* spr registers 1537-1550 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */ + + /* spr registers 1552-1663 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* IAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* IAMLR7 */ + + /* spr registers 1672-1727 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, /* IAMPR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, /* IAMPR7 */ + + /* spr registers 1736-1791 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* DAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* DAMLR11 */ + + /* spr registers 1804-1855 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, /* DAMPR0 */ + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP}, /* DAMPR11 */ + + /* spr registers 1868-1919 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000808, 0x00000808, 0x00000808, 0xffffffff, IMPL, SUP}, /* AMCR */ + + /* spr registers 1921-1924 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffff00, IMPL, SUP}, /* IAMVR1 */ + RESERVED, + {0x00000000, 0x00000000, 0x00000000, 0xfffff000, IMPL, SUP}, /* DAMVR1 */ + + /* spr registers 1928-1935 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xfffff000, IMPL, SUP}, /* CXNR */ + {0x00000000, 0x00000000, 0x00000000, 0x000007fc, IMPL, SUP}, /* TTBR */ + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* TPLR */ + {0x00000000, 0x00000000, 0x00000000, 0x000031f0, IMPL, SUP}, /* TPPR */ + {0x00000000, 0x00000000, 0x00000000, 0x0fffffff, IMPL, SUP}, /* TPXR */ + + /* spr registers 1941-1951 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* TIMERH */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* TIMERL */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* TIMERD */ + + /* spr registers 1955-2047 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DCR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* BRR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* NMAR */ + + {0x00000000, 0x00000000, 0x00000000, 0x00000ffe, IMPL, SUP}, /* BTBR */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR3 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR2 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR02 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* spr registers 2066-2075 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* spr registers 2078 and 2079 are reserved */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* spr registers 2082-4095 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, +}; + /* Initialize register control for this cpu */ void frv_register_control_init (SIM_CPU *cpu) @@ -5311,6 +6352,8 @@ frv_register_control_init (SIM_CPU *cpu) if (sizeof (fr400_spr) != FRV_MAX_SPR * sizeof (*fr400_spr)) abort (); + if (sizeof (fr450_spr) != FRV_MAX_SPR * sizeof (*fr450_spr)) + abort (); if (sizeof (fr500_spr) != FRV_MAX_SPR * sizeof (*fr500_spr)) abort (); if (sizeof (fr550_spr) != FRV_MAX_SPR * sizeof (*fr550_spr)) @@ -5331,6 +6374,11 @@ frv_register_control_init (SIM_CPU *cpu) control->cpr = 0; control->spr = fr550_spr; return; + case bfd_mach_fr450: + control->fr = 1; + control->cpr = 0; + control->spr = fr450_spr; + return; case bfd_mach_fr400: control->fr = 1; control->cpr = 0; @@ -5449,11 +6497,11 @@ frv_check_spr_read_access (SIM_CPU *current_cpu, UINT spr) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: - /* On the fr400: if this is an unimplemented accumulator, then - generate an illegal_instruction_interrupt, otherwise no interrupt. - */ - if (spr >= H_SPR_ACC4 && spr <= H_SPR_ACC63 - || spr >= H_SPR_ACCG4 && spr <= H_SPR_ACCG63) + case bfd_mach_fr450: + /* On the fr4xx series: if this is an unimplemented accumulator, + then generate an illegal_instruction_interrupt, otherwise no + interrupt. */ + if (SPR_IS_ACC (spr)) frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; case bfd_mach_fr550: @@ -5542,6 +6590,7 @@ frv_check_register_access ( switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: /* On some machines this generates an illegal_instruction interrupt. */ frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); diff --git a/sim/frv/sem.c b/sim/frv/sem.c index 4f2883b..0fb30c3 100644 --- a/sim/frv/sem.c +++ b/sim/frv/sem.c @@ -5630,138 +5630,6 @@ frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FL #undef FLD } -/* rstb: rstb$pack $GRk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 1, 0); -} - - return vpc; -#undef FLD -} - -/* rsth: rsth$pack $GRk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 2, 0); -} - - return vpc; -#undef FLD -} - -/* rst: rst$pack $GRk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rst) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 4, 0); -} - - return vpc; -#undef FLD -} - -/* rstbf: rstbf$pack $FRintk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 1, 1); -} - - return vpc; -#undef FLD -} - -/* rsthf: rsthf$pack $FRintk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rsthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 2, 1); -} - - return vpc; -#undef FLD -} - -/* rstf: rstf$pack $FRintk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 4, 1); -} - - return vpc; -#undef FLD -} - /* std: std$pack $GRdoublek,@($GRi,$GRj) */ static SEM_PC @@ -5831,54 +5699,6 @@ frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_CPR_DOUBLE (FLD (f_CPRk) #undef FLD } -/* rstd: rstd$pack $GRdoublek,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; -{ - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk))); -} -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 8, 0); -} - - return vpc; -#undef FLD -} - -/* rstdf: rstdf$pack $FRdoublek,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; -{ - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk))); -} -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 8, 1); -} - - return vpc; -#undef FLD -} - /* stq: stq$pack $GRk,@($GRi,$GRj) */ static SEM_PC @@ -5948,54 +5768,6 @@ frvbf_store_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk)); #undef FLD } -/* rstq: rstq$pack $GRk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; -{ - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); -} -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 16, 0); -} - - return vpc; -#undef FLD -} - -/* rstqf: rstqf$pack $FRintk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; -{ - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); -} -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 16, 1); -} - - return vpc; -#undef FLD -} - /* stbu: stbu$pack $GRk,@($GRi,$GRj) */ static SEM_PC @@ -16632,6 +16404,57 @@ SEM_FN_NAME (frvbf,membar) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #undef FLD } +/* lrai: lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ + +static SEM_PC +SEM_FN_NAME (frvbf,lrai) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* lrad: lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ + +static SEM_PC +SEM_FN_NAME (frvbf,lrad) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* tlbpr: tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */ + +static SEM_PC +SEM_FN_NAME (frvbf,tlbpr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + /* cop1: cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */ static SEM_PC @@ -22836,6 +22659,270 @@ frvbf_media_overflow (current_cpu, 1); #undef FLD } +/* mqlclrhs: mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqlclrhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_a1; + HI tmp_a2; + HI tmp_a3; + HI tmp_a4; + HI tmp_b1; + HI tmp_b2; + HI tmp_b3; + HI tmp_b4; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_a1 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_a2 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_b1 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_b2 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + tmp_a3 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_a4 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_b3 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_b4 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + UHI opval = (LEUHI (ABSHI (tmp_a1), ABSHI (tmp_b1))) ? (0) : (LEHI (0, tmp_b1)) ? (tmp_a1) : (EQHI (tmp_a1, -32768)) ? (32767) : (NEGHI (tmp_a1)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = (LEUHI (ABSHI (tmp_a2), ABSHI (tmp_b2))) ? (0) : (LEHI (0, tmp_b2)) ? (tmp_a2) : (EQHI (tmp_a2, -32768)) ? (32767) : (NEGHI (tmp_a2)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = (LEUHI (ABSHI (tmp_a3), ABSHI (tmp_b3))) ? (0) : (LEHI (0, tmp_b3)) ? (tmp_a3) : (EQHI (tmp_a3, -32768)) ? (32767) : (NEGHI (tmp_a3)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = (LEUHI (ABSHI (tmp_a4), ABSHI (tmp_b4))) ? (0) : (LEHI (0, tmp_b4)) ? (tmp_a4) : (EQHI (tmp_a4, -32768)) ? (32767) : (NEGHI (tmp_a4)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqlmths: mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqlmths) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_a1; + HI tmp_a2; + HI tmp_a3; + HI tmp_a4; + HI tmp_b1; + HI tmp_b2; + HI tmp_b3; + HI tmp_b4; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_a1 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_a2 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_b1 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_b2 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + tmp_a3 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_a4 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_b3 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_b4 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + UHI opval = (ANDIF (GTHI (tmp_b1, -32768), GEHI (tmp_a1, ABSHI (tmp_b1)))) ? (tmp_b1) : (GTHI (tmp_a1, NEGHI (ABSHI (tmp_b1)))) ? (tmp_a1) : (EQHI (tmp_b1, -32768)) ? (32767) : (NEGHI (tmp_b1)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = (ANDIF (GTHI (tmp_b2, -32768), GEHI (tmp_a2, ABSHI (tmp_b2)))) ? (tmp_b2) : (GTHI (tmp_a2, NEGHI (ABSHI (tmp_b2)))) ? (tmp_a2) : (EQHI (tmp_b2, -32768)) ? (32767) : (NEGHI (tmp_b2)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = (ANDIF (GTHI (tmp_b3, -32768), GEHI (tmp_a3, ABSHI (tmp_b3)))) ? (tmp_b3) : (GTHI (tmp_a3, NEGHI (ABSHI (tmp_b3)))) ? (tmp_a3) : (EQHI (tmp_b3, -32768)) ? (32767) : (NEGHI (tmp_b3)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = (ANDIF (GTHI (tmp_b4, -32768), GEHI (tmp_a4, ABSHI (tmp_b4)))) ? (tmp_b4) : (GTHI (tmp_a4, NEGHI (ABSHI (tmp_b4)))) ? (tmp_a4) : (EQHI (tmp_b4, -32768)) ? (32767) : (NEGHI (tmp_b4)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqsllhi: mqsllhi$pack $FRintieven,$u6,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqsllhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqsrahi: mqsrahi$pack $FRintieven,$u6,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqsrahi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + /* maddaccs: maddaccs$pack $ACC40Si,$ACC40Sk */ static SEM_PC @@ -28264,22 +28351,12 @@ static const struct sem_fn_desc sem_fns[] = { { FRVBF_INSN_STHF, SEM_FN_NAME (frvbf,sthf) }, { FRVBF_INSN_STF, SEM_FN_NAME (frvbf,stf) }, { FRVBF_INSN_STC, SEM_FN_NAME (frvbf,stc) }, - { FRVBF_INSN_RSTB, SEM_FN_NAME (frvbf,rstb) }, - { FRVBF_INSN_RSTH, SEM_FN_NAME (frvbf,rsth) }, - { FRVBF_INSN_RST, SEM_FN_NAME (frvbf,rst) }, - { FRVBF_INSN_RSTBF, SEM_FN_NAME (frvbf,rstbf) }, - { FRVBF_INSN_RSTHF, SEM_FN_NAME (frvbf,rsthf) }, - { FRVBF_INSN_RSTF, SEM_FN_NAME (frvbf,rstf) }, { FRVBF_INSN_STD, SEM_FN_NAME (frvbf,std) }, { FRVBF_INSN_STDF, SEM_FN_NAME (frvbf,stdf) }, { FRVBF_INSN_STDC, SEM_FN_NAME (frvbf,stdc) }, - { FRVBF_INSN_RSTD, SEM_FN_NAME (frvbf,rstd) }, - { FRVBF_INSN_RSTDF, SEM_FN_NAME (frvbf,rstdf) }, { FRVBF_INSN_STQ, SEM_FN_NAME (frvbf,stq) }, { FRVBF_INSN_STQF, SEM_FN_NAME (frvbf,stqf) }, { FRVBF_INSN_STQC, SEM_FN_NAME (frvbf,stqc) }, - { FRVBF_INSN_RSTQ, SEM_FN_NAME (frvbf,rstq) }, - { FRVBF_INSN_RSTQF, SEM_FN_NAME (frvbf,rstqf) }, { FRVBF_INSN_STBU, SEM_FN_NAME (frvbf,stbu) }, { FRVBF_INSN_STHU, SEM_FN_NAME (frvbf,sthu) }, { FRVBF_INSN_STU, SEM_FN_NAME (frvbf,stu) }, @@ -28619,6 +28696,9 @@ static const struct sem_fn_desc sem_fns[] = { { FRVBF_INSN_DCUL, SEM_FN_NAME (frvbf,dcul) }, { FRVBF_INSN_BAR, SEM_FN_NAME (frvbf,bar) }, { FRVBF_INSN_MEMBAR, SEM_FN_NAME (frvbf,membar) }, + { FRVBF_INSN_LRAI, SEM_FN_NAME (frvbf,lrai) }, + { FRVBF_INSN_LRAD, SEM_FN_NAME (frvbf,lrad) }, + { FRVBF_INSN_TLBPR, SEM_FN_NAME (frvbf,tlbpr) }, { FRVBF_INSN_COP1, SEM_FN_NAME (frvbf,cop1) }, { FRVBF_INSN_COP2, SEM_FN_NAME (frvbf,cop2) }, { FRVBF_INSN_CLRGR, SEM_FN_NAME (frvbf,clrgr) }, @@ -28766,6 +28846,10 @@ static const struct sem_fn_desc sem_fns[] = { { FRVBF_INSN_CMQADDHUS, SEM_FN_NAME (frvbf,cmqaddhus) }, { FRVBF_INSN_CMQSUBHSS, SEM_FN_NAME (frvbf,cmqsubhss) }, { FRVBF_INSN_CMQSUBHUS, SEM_FN_NAME (frvbf,cmqsubhus) }, + { FRVBF_INSN_MQLCLRHS, SEM_FN_NAME (frvbf,mqlclrhs) }, + { FRVBF_INSN_MQLMTHS, SEM_FN_NAME (frvbf,mqlmths) }, + { FRVBF_INSN_MQSLLHI, SEM_FN_NAME (frvbf,mqsllhi) }, + { FRVBF_INSN_MQSRAHI, SEM_FN_NAME (frvbf,mqsrahi) }, { FRVBF_INSN_MADDACCS, SEM_FN_NAME (frvbf,maddaccs) }, { FRVBF_INSN_MSUBACCS, SEM_FN_NAME (frvbf,msubaccs) }, { FRVBF_INSN_MDADDACCS, SEM_FN_NAME (frvbf,mdaddaccs) }, diff --git a/sim/frv/traps.c b/sim/frv/traps.c index f7b4b74..3e93446 100644 --- a/sim/frv/traps.c +++ b/sim/frv/traps.c @@ -50,7 +50,8 @@ frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, { if (sig == sim_core_unaligned_signal) { - if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 + || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) frv_queue_data_access_error_interrupt (current_cpu, addr); else frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr); @@ -591,7 +592,13 @@ frvbf_media_cr_not_aligned (SIM_CPU *current_cpu) /* On some machines this generates an illegal_instruction interrupt. */ switch (STATE_ARCHITECTURE (sd)->mach) { + /* Note: there is a discrepancy between V2.2 of the FR400 + instruction manual and the various FR4xx LSI specs. The former + claims that unaligned registers cause an mp_exception while the + latter say it's an illegal_instruction. The LSI specs appear + to be correct since MTT is fixed at 1. */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; @@ -610,7 +617,9 @@ frvbf_media_acc_not_aligned (SIM_CPU *current_cpu) /* On some machines this generates an illegal_instruction interrupt. */ switch (STATE_ARCHITECTURE (sd)->mach) { + /* See comment in frvbf_cr_not_aligned(). */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; @@ -629,7 +638,9 @@ frvbf_media_register_not_aligned (SIM_CPU *current_cpu) /* On some machines this generates an illegal_instruction interrupt. */ switch (STATE_ARCHITECTURE (sd)->mach) { + /* See comment in frvbf_cr_not_aligned(). */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index 4e7b230..a344a6d 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,31 @@ +2004-03-01 Richard Sandiford <rsandifo@redhat.com> + + * sim/frv/allinsn.exp (all_machs): Add fr405 and fr450. + * sim/fr400/allinsn.exp (all_machs): Likewise. + * sim/fr400/addss.cgs (mach): Change to "fr405 fr450". + * sim/fr400/scutss.cgs (mach): Likewise. + * sim/fr400/slass.cgs (mach): Likewise. + * sim/fr400/smass.cgs (mach): Likewise. + * sim/fr400/smsss.cgs (mach): Likewise. + * sim/fr400/smu.cgs (mach): Likewise. + * sim/fr400/subss.cgs (mach): Likewise. + * sim/interrupts/fp_exception.cgs: Replace fmadds with .word. + * sim/interrupts/fp_exception-fr550.cgs: Likewise. + * sim/frv/mqlclrhs.cgs: New test. + * sim/frv/mqlmths.cgs: New test. + * sim/frv/mqsllhi.cgs: New test. + * sim/frv/mqsrahi.cgs: New test. + +2004-03-01 Richard Sandiford <rsandifo@redhat.com> + + * sim/frv/fr400/scutss.cgs: Fix tests to account for rounding. + Add some new ones. + +2004-03-01 Richard Sandiford <rsandifo@redhat.com> + + * sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete. + * sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete. + 2004-01-26 Chris Demetriou <cgd@broadcom.com> * sim/mips: New directory. Tests for the MIPS simulator. diff --git a/sim/testsuite/sim/frv/allinsn.exp b/sim/testsuite/sim/frv/allinsn.exp index 220550d..b7f9fe2 100644 --- a/sim/testsuite/sim/frv/allinsn.exp +++ b/sim/testsuite/sim/frv/allinsn.exp @@ -4,7 +4,7 @@ if [istarget frv*-*] { # load support procs (none yet) # load_lib cgen.exp # all machines - set all_machs "frv fr500 fr550 fr400" + set all_machs "frv fr500 fr550 fr400 fr405 fr450" set cpu_option -mcpu # The .cgs suffix is for "cgen .s". diff --git a/sim/testsuite/sim/frv/fr400/addss.cgs b/sim/testsuite/sim/frv/fr400/addss.cgs index 631d574..b108f50 100644 --- a/sim/testsuite/sim/frv/fr400/addss.cgs +++ b/sim/testsuite/sim/frv/fr400/addss.cgs @@ -1,5 +1,5 @@ # frv testcase for addss $GRi,$GRj,$GRk -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/allinsn.exp b/sim/testsuite/sim/frv/fr400/allinsn.exp index 53394ec..b169761 100644 --- a/sim/testsuite/sim/frv/fr400/allinsn.exp +++ b/sim/testsuite/sim/frv/fr400/allinsn.exp @@ -4,7 +4,7 @@ if [istarget frv*-*] { # load support procs (none yet) # load_lib cgen.exp # all machines - set all_machs "fr400 fr550" + set all_machs "fr400 fr405 fr450 fr550" set cpu_option -mcpu # The .cgs suffix is for "cgen .s". diff --git a/sim/testsuite/sim/frv/fr400/scutss.cgs b/sim/testsuite/sim/frv/fr400/scutss.cgs index aa115b9..f958de6 100644 --- a/sim/testsuite/sim/frv/fr400/scutss.cgs +++ b/sim/testsuite/sim/frv/fr400/scutss.cgs @@ -1,5 +1,5 @@ # frv testcase for scutss $FRj,$FRk -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" @@ -12,7 +12,7 @@ scutss: set_gr_immed 0,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe7,gr11 + test_gr_limmed 0xffff,0xffe8,gr11 set_gr_immed 1,gr10 scutss gr10,gr11 @@ -28,7 +28,7 @@ scutss: set_gr_immed 4,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xfe78,gr11 + test_gr_limmed 0xffff,0xfe79,gr11 set_gr_immed 5,gr10 scutss gr10,gr11 @@ -40,11 +40,11 @@ scutss: set_gr_immed 7,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xf3c4,gr11 + test_gr_limmed 0xffff,0xf3c5,gr11 set_gr_immed 8,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xe789,gr11 + test_gr_limmed 0xffff,0xe78a,gr11 set_gr_immed 9,gr10 scutss gr10,gr11 @@ -52,7 +52,7 @@ scutss: set_gr_immed 10,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0x9e26,gr11 + test_gr_limmed 0xffff,0x9e27,gr11 set_gr_immed 11,gr10 scutss gr10,gr11 @@ -60,7 +60,7 @@ scutss: set_gr_immed 12,gr10 scutss gr10,gr11 - test_gr_limmed 0xfffe,0x789a,gr11 + test_gr_limmed 0xfffe,0x789b,gr11 set_gr_immed 13,gr10 scutss gr10,gr11 @@ -68,19 +68,19 @@ scutss: set_gr_immed 14,gr10 scutss gr10,gr11 - test_gr_limmed 0xfff9,0xe26a,gr11 + test_gr_limmed 0xfff9,0xe26b,gr11 set_gr_immed 15,gr10 scutss gr10,gr11 - test_gr_limmed 0xfff3,0xc4d5,gr11 + test_gr_limmed 0xfff3,0xc4d6,gr11 set_gr_immed 16,gr10 scutss gr10,gr11 - test_gr_limmed 0xffe7,0x89ab,gr11 + test_gr_limmed 0xffe7,0x89ac,gr11 set_gr_immed 17,gr10 scutss gr10,gr11 - test_gr_limmed 0xffcf,0x1357,gr11 + test_gr_limmed 0xffcf,0x1358,gr11 set_gr_immed 18,gr10 scutss gr10,gr11 @@ -92,11 +92,11 @@ scutss: set_gr_immed 20,gr10 scutss gr10,gr11 - test_gr_limmed 0xfe78,0x9abc,gr11 + test_gr_limmed 0xfe78,0x9abd,gr11 set_gr_immed 21,gr10 scutss gr10,gr11 - test_gr_limmed 0xfcf1,0x3579,gr11 + test_gr_limmed 0xfcf1,0x357a,gr11 set_gr_immed 22,gr10 scutss gr10,gr11 @@ -104,19 +104,19 @@ scutss: set_gr_immed 23,gr10 scutss gr10,gr11 - test_gr_limmed 0xf3c4,0xd5e6,gr11 + test_gr_limmed 0xf3c4,0xd5e7,gr11 set_gr_immed 24,gr10 scutss gr10,gr11 - test_gr_limmed 0xe789,0xabcd,gr11 + test_gr_limmed 0xe789,0xabce,gr11 set_gr_immed 25,gr10 scutss gr10,gr11 - test_gr_limmed 0xcf13,0x579b,gr11 + test_gr_limmed 0xcf13,0x579c,gr11 set_gr_immed 26,gr10 scutss gr10,gr11 - test_gr_limmed 0x9e26,0xaf37,gr11 + test_gr_limmed 0x9e26,0xaf38,gr11 set_gr_immed 27,gr10 scutss gr10,gr11 @@ -268,11 +268,11 @@ scutss: set_gr_immed 64,gr10 ; same as -64 scutss gr10,gr11 - test_gr_immed -1,gr11 + test_gr_immed 0,gr11 set_gr_immed 128,gr10 ; same as 0 scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe7,gr11 + test_gr_limmed 0xffff,0xffe8,gr11 .global scutss2 scutss2: @@ -281,7 +281,7 @@ scutss2: set_gr_limmed 0xffff,0xffff,gr10 ; -1 scutss gr10,gr11 - test_gr_limmed 0xf3c4,0xd5e6,gr11 + test_gr_limmed 0xf3c4,0xd5e7,gr11 set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) scutss gr10,gr11 @@ -289,11 +289,11 @@ scutss2: set_gr_immed -3,gr10 scutss gr10,gr11 - test_gr_limmed 0xfcf1,0x3579,gr11 + test_gr_limmed 0xfcf1,0x357a,gr11 set_gr_immed -4,gr10 scutss gr10,gr11 - test_gr_limmed 0xfe78,0x9abc,gr11 + test_gr_limmed 0xfe78,0x9abd,gr11 set_gr_immed -5,gr10 scutss gr10,gr11 @@ -305,19 +305,19 @@ scutss2: set_gr_immed -7,gr10 scutss gr10,gr11 - test_gr_limmed 0xffcf,0x1357,gr11 + test_gr_limmed 0xffcf,0x1358,gr11 set_gr_immed -8,gr10 scutss gr10,gr11 - test_gr_limmed 0xffe7,0x89ab,gr11 + test_gr_limmed 0xffe7,0x89ac,gr11 set_gr_immed -9,gr10 scutss gr10,gr11 - test_gr_limmed 0xfff3,0xc4d5,gr11 + test_gr_limmed 0xfff3,0xc4d6,gr11 set_gr_immed -10,gr10 scutss gr10,gr11 - test_gr_limmed 0xfff9,0xe26a,gr11 + test_gr_limmed 0xfff9,0xe26b,gr11 set_gr_immed -11,gr10 scutss gr10,gr11 @@ -325,7 +325,7 @@ scutss2: set_gr_immed -12,gr10 scutss gr10,gr11 - test_gr_limmed 0xfffe,0x789a,gr11 + test_gr_limmed 0xfffe,0x789b,gr11 set_gr_immed -13,gr10 scutss gr10,gr11 @@ -333,7 +333,7 @@ scutss2: set_gr_immed -14,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0x9e26,gr11 + test_gr_limmed 0xffff,0x9e27,gr11 set_gr_immed -15,gr10 scutss gr10,gr11 @@ -341,11 +341,11 @@ scutss2: set_gr_immed -16,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xe789,gr11 + test_gr_limmed 0xffff,0xe78a,gr11 set_gr_immed -17,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xf3c4,gr11 + test_gr_limmed 0xffff,0xf3c5,gr11 set_gr_immed -18,gr10 scutss gr10,gr11 @@ -357,7 +357,7 @@ scutss2: set_gr_immed -20,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xfe78,gr11 + test_gr_limmed 0xffff,0xfe79,gr11 set_gr_immed -21,gr10 scutss gr10,gr11 @@ -373,19 +373,19 @@ scutss2: set_gr_immed -24,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe7,gr11 + test_gr_limmed 0xffff,0xffe8,gr11 set_gr_immed -25,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xfff3,gr11 + test_gr_limmed 0xffff,0xfff4,gr11 set_gr_immed -26,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xfff9,gr11 + test_gr_limmed 0xffff,0xfffa,gr11 set_gr_immed -27,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xfffc,gr11 + test_gr_limmed 0xffff,0xfffd,gr11 set_gr_immed -28,gr10 scutss gr10,gr11 @@ -397,26 +397,26 @@ scutss2: set_gr_immed -30,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 + test_gr_immed 0,gr11 set_gr_immed -31,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 + test_gr_immed 0,gr11 set_gr_immed -32,gr10 scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 + test_gr_immed 0,gr11 set_gr_limmed 0,64,gr10 ; same as -32 scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 + test_gr_immed 0,gr11 set_spr_immed 0x6789abcd,iacc0h set_spr_immed 0xefa5a5a5,iacc0l set_gr_limmed 0xffff,0xffff,gr10 scutss gr10,gr11 - test_gr_limmed 0x33c4,0xd5e6,gr11 + test_gr_limmed 0x33c4,0xd5e7,gr11 set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) scutss gr10,gr11 @@ -424,11 +424,11 @@ scutss2: set_gr_immed -3,gr10 scutss gr10,gr11 - test_gr_limmed 0x0cf1,0x3579,gr11 + test_gr_limmed 0x0cf1,0x357a,gr11 set_gr_immed -4,gr10 scutss gr10,gr11 - test_gr_limmed 0x0678,0x9abc,gr11 + test_gr_limmed 0x0678,0x9abd,gr11 set_gr_immed -5,gr10 scutss gr10,gr11 @@ -440,19 +440,19 @@ scutss2: set_gr_immed -7,gr10 scutss gr10,gr11 - test_gr_limmed 0x00cf,0x1357,gr11 + test_gr_limmed 0x00cf,0x1358,gr11 set_gr_immed -8,gr10 scutss gr10,gr11 - test_gr_limmed 0x0067,0x89ab,gr11 + test_gr_limmed 0x0067,0x89ac,gr11 set_gr_immed -9,gr10 scutss gr10,gr11 - test_gr_limmed 0x0033,0xc4d5,gr11 + test_gr_limmed 0x0033,0xc4d6,gr11 set_gr_immed -10,gr10 scutss gr10,gr11 - test_gr_limmed 0x0019,0xe26a,gr11 + test_gr_limmed 0x0019,0xe26b,gr11 set_gr_immed -11,gr10 scutss gr10,gr11 @@ -460,7 +460,7 @@ scutss2: set_gr_immed -12,gr10 scutss gr10,gr11 - test_gr_limmed 0x0006,0x789a,gr11 + test_gr_limmed 0x0006,0x789b,gr11 set_gr_immed -13,gr10 scutss gr10,gr11 @@ -468,7 +468,7 @@ scutss2: set_gr_immed -14,gr10 scutss gr10,gr11 - test_gr_limmed 0x0001,0x9e26,gr11 + test_gr_limmed 0x0001,0x9e27,gr11 set_gr_immed -15,gr10 scutss gr10,gr11 @@ -476,11 +476,11 @@ scutss2: set_gr_immed -16,gr10 scutss gr10,gr11 - test_gr_limmed 0x0000,0x6789,gr11 + test_gr_limmed 0x0000,0x678a,gr11 set_gr_immed -17,gr10 scutss gr10,gr11 - test_gr_limmed 0x0000,0x33c4,gr11 + test_gr_limmed 0x0000,0x33c5,gr11 set_gr_immed -18,gr10 scutss gr10,gr11 @@ -492,7 +492,7 @@ scutss2: set_gr_immed -20,gr10 scutss gr10,gr11 - test_gr_limmed 0x0000,0x0678,gr11 + test_gr_limmed 0x0000,0x0679,gr11 set_gr_immed -21,gr10 scutss gr10,gr11 @@ -508,19 +508,19 @@ scutss2: set_gr_immed -24,gr10 scutss gr10,gr11 - test_gr_limmed 0x0000,0x0067,gr11 + test_gr_limmed 0x0000,0x0068,gr11 set_gr_immed -25,gr10 scutss gr10,gr11 - test_gr_limmed 0x0000,0x0033,gr11 + test_gr_limmed 0x0000,0x0034,gr11 set_gr_immed -26,gr10 scutss gr10,gr11 - test_gr_limmed 0x0000,0x0019,gr11 + test_gr_limmed 0x0000,0x001a,gr11 set_gr_immed -27,gr10 scutss gr10,gr11 - test_gr_limmed 0x0000,0x000c,gr11 + test_gr_limmed 0x0000,0x000d,gr11 set_gr_immed -28,gr10 scutss gr10,gr11 @@ -532,11 +532,11 @@ scutss2: set_gr_immed -30,gr10 scutss gr10,gr11 - test_gr_limmed 0x0000,0x0001,gr11 + test_gr_limmed 0x0000,0x0002,gr11 set_gr_immed -31,gr10 scutss gr10,gr11 - test_gr_limmed 0x0000,0x0000,gr11 + test_gr_limmed 0x0000,0x0001,gr11 set_gr_immed -32,gr10 scutss gr10,gr11 @@ -630,13 +630,35 @@ scutss2: set_gr_limmed 0xffff,0xfffc,gr10 scutss gr10,gr11 - test_gr_limmed 0xfaf5,0xa5a5,gr11 + test_gr_limmed 0xfaf5,0xa5a6,gr11 set_spr_immed 0x2f5a5a5a,iacc0h set_spr_immed 0x5a5a5a5a,iacc0l set_gr_limmed 0xffff,0xfff9,gr10 scutss gr10,gr11 - test_gr_limmed 0x005e,0xb4b4,gr11 + test_gr_limmed 0x005e,0xb4b5,gr11 + +# From the manual + .global scutss3 +scutss3: + set_spr_immed 0xfffffedc,iacc0h + set_spr_immed 0xba987654,iacc0l + + set_gr_immed 16,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfedc,0xba98,gr11 + + set_gr_immed 12,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffed,0xcbaa,gr11 + + set_gr_immed -4,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffee,gr11 + + set_gr_immed 24,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 pass diff --git a/sim/testsuite/sim/frv/fr400/slass.cgs b/sim/testsuite/sim/frv/fr400/slass.cgs index 0100052..3e8bcac 100644 --- a/sim/testsuite/sim/frv/fr400/slass.cgs +++ b/sim/testsuite/sim/frv/fr400/slass.cgs @@ -1,5 +1,5 @@ # frv testcase for slass $GRi,$GRj,$GRk -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/smass.cgs b/sim/testsuite/sim/frv/fr400/smass.cgs index 3df0fa5..4594ecd 100644 --- a/sim/testsuite/sim/frv/fr400/smass.cgs +++ b/sim/testsuite/sim/frv/fr400/smass.cgs @@ -1,5 +1,5 @@ # frv testcase for smass $GRi,$GRj -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/smsss.cgs b/sim/testsuite/sim/frv/fr400/smsss.cgs index 56efa56..50876d8 100644 --- a/sim/testsuite/sim/frv/fr400/smsss.cgs +++ b/sim/testsuite/sim/frv/fr400/smsss.cgs @@ -1,5 +1,5 @@ # frv testcase for smsss $GRi,$GRj -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/smu.cgs b/sim/testsuite/sim/frv/fr400/smu.cgs index d0087df..eae788e 100644 --- a/sim/testsuite/sim/frv/fr400/smu.cgs +++ b/sim/testsuite/sim/frv/fr400/smu.cgs @@ -1,5 +1,5 @@ # frv testcase for smu $GRi,$GRj -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/subss.cgs b/sim/testsuite/sim/frv/fr400/subss.cgs index cbaafb5..fcda589 100644 --- a/sim/testsuite/sim/frv/fr400/subss.cgs +++ b/sim/testsuite/sim/frv/fr400/subss.cgs @@ -1,5 +1,5 @@ # frv testcase for subss $GRi,$GRj,$GRk -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs index 0bb98d8..5d1c3f5 100644 --- a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs +++ b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs @@ -70,7 +70,7 @@ pack: fnegs fr10,fr12 set_spr_addr ok1,lr set_gr_immed 4,gr20 ; PC increment -bad: fmadds fr16,fr4,fr1 ; unimplemented +bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) test_gr_immed 4,gr15 and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs index ad5f7e4..0109b53 100644 --- a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs +++ b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs @@ -65,7 +65,7 @@ pack: fnegs fr10,fr10 set_spr_addr ok1,lr set_gr_immed 4,gr20 ; PC increment -bad: fmadds fr16,fr4,fr1 ; unimplemented +bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) test_gr_immed 4,gr15 and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception diff --git a/sim/testsuite/sim/frv/mqlclrhs.cgs b/sim/testsuite/sim/frv/mqlclrhs.cgs new file mode 100644 index 0000000..5e090b0 --- /dev/null +++ b/sim/testsuite/sim/frv/mqlclrhs.cgs @@ -0,0 +1,74 @@ +# frv testcase for mqlclrhs $FRi,$FRj,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqlclrhs +mqlclrhs: + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0x0800,0x0800,fr6 + set_fr_iimmed 0x0800,0x0800,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x1000,0x2000,fr8 + test_fr_limmed 0xe800,0xd800,fr9 + + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0xf800,0xf800,fr6 + set_fr_iimmed 0xf800,0xf800,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0xf000,0xe000,fr8 + test_fr_limmed 0x1800,0x2800,fr9 + + set_fr_iimmed 0x1000,0x1000,fr4 + set_fr_iimmed 0x1000,0x1000,fr5 + set_fr_iimmed 0xf000,0xf800,fr6 + set_fr_iimmed 0x0800,0x1000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0xf000,fr8 + test_fr_limmed 0x1000,0x0000,fr9 + + set_fr_iimmed 0xf000,0xf000,fr4 + set_fr_iimmed 0xf000,0xf000,fr5 + set_fr_iimmed 0xf000,0xf800,fr6 + set_fr_iimmed 0x0800,0x1000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x1000,fr8 + test_fr_limmed 0xf000,0x0000,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x8000,0x8000,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x8000,fr8 + test_fr_limmed 0x7fff,0x8000,fr9 + + set_fr_iimmed 0x7fff,0x7fff,fr4 + set_fr_iimmed 0x7fff,0x7fff,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_fr_limmed 0x0000,0x7fff,fr9 + + set_fr_iimmed 0x8001,0x8001,fr4 + set_fr_iimmed 0x8001,0x8001,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_fr_limmed 0x0000,0x8001,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x0001,0xffff,fr5 + set_fr_iimmed 0x0001,0xffff,fr6 + set_fr_iimmed 0x8000,0x8000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x8000,0x7fff,fr8 + test_fr_limmed 0x0000,0x0000,fr9 + + pass diff --git a/sim/testsuite/sim/frv/mqlmths.cgs b/sim/testsuite/sim/frv/mqlmths.cgs new file mode 100644 index 0000000..d416d65 --- /dev/null +++ b/sim/testsuite/sim/frv/mqlmths.cgs @@ -0,0 +1,74 @@ +# frv testcase for mqlmths $FRi,$FRj,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqlmths +mqlmths: + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0x0800,0x0800,fr6 + set_fr_iimmed 0x0800,0x0800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x0800,0x0800,fr8 + test_fr_limmed 0xf800,0xf800,fr9 + + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0xf800,0xf800,fr6 + set_fr_iimmed 0xf800,0xf800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0xf800,0xf800,fr8 + test_fr_limmed 0x0800,0x0800,fr9 + + set_fr_iimmed 0x1000,0x1000,fr4 + set_fr_iimmed 0x1000,0x1000,fr5 + set_fr_iimmed 0xe800,0xf800,fr6 + set_fr_iimmed 0x0800,0x1800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x1000,0xf800,fr8 + test_fr_limmed 0x0800,0x1000,fr9 + + set_fr_iimmed 0xf000,0xf000,fr4 + set_fr_iimmed 0xf000,0xf000,fr5 + set_fr_iimmed 0xe800,0xf800,fr6 + set_fr_iimmed 0x0800,0x1800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0xf000,0x0800,fr8 + test_fr_limmed 0xf800,0xf000,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x8000,0x8000,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x7fff,0x8001,fr8 + test_fr_limmed 0x7fff,0x0000,fr9 + + set_fr_iimmed 0x7fff,0x7fff,fr4 + set_fr_iimmed 0x7fff,0x7fff,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x7fff,0x7fff,fr8 + test_fr_limmed 0x8001,0x0000,fr9 + + set_fr_iimmed 0x8001,0x8001,fr4 + set_fr_iimmed 0x8001,0x8001,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x8001,0x8001,fr8 + test_fr_limmed 0x7fff,0x0000,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x0001,0xffff,fr5 + set_fr_iimmed 0x0001,0xffff,fr6 + set_fr_iimmed 0x8000,0x8000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0xffff,0x0001,fr8 + test_fr_limmed 0x0001,0xffff,fr9 + + pass diff --git a/sim/testsuite/sim/frv/mqsllhi.cgs b/sim/testsuite/sim/frv/mqsllhi.cgs new file mode 100644 index 0000000..21379f2 --- /dev/null +++ b/sim/testsuite/sim/frv/mqsllhi.cgs @@ -0,0 +1,40 @@ +# frv testcase for mqsllhi $FRi,#u6,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqsllhi +mqsllhi: + set_fr_iimmed 0x0001,0x0002,fr4 + set_fr_iimmed 0x0003,0x0004,fr5 + mqsllhi fr4,#1,fr6 + test_fr_limmed 0x0002,0x0004,fr6 + test_fr_limmed 0x0006,0x0008,fr7 + + set_fr_iimmed 0xffff,0xfffe,fr4 + set_fr_iimmed 0xfffc,0xfff8,fr5 + mqsllhi fr4,#1,fr6 + test_fr_limmed 0xfffe,0xfffc,fr6 + test_fr_limmed 0xfff8,0xfff0,fr7 + + set_fr_iimmed 0xffff,0xfffe,fr4 + set_fr_iimmed 0xfffc,0xfff8,fr5 + mqsllhi fr4,#12,fr6 + test_fr_limmed 0xf000,0xe000,fr6 + test_fr_limmed 0xc000,0x8000,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsllhi fr4,#12,fr6 + test_fr_limmed 0x4000,0x8000,fr6 + test_fr_limmed 0xc000,0x0000,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsllhi fr4,#16,fr6 + test_fr_limmed 0x1234,0x5678,fr6 + test_fr_limmed 0x9abc,0xdef0,fr7 + + pass diff --git a/sim/testsuite/sim/frv/mqsrahi.cgs b/sim/testsuite/sim/frv/mqsrahi.cgs new file mode 100644 index 0000000..1d30179 --- /dev/null +++ b/sim/testsuite/sim/frv/mqsrahi.cgs @@ -0,0 +1,40 @@ +# frv testcase for mqsrahi $FRi,#u6,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqsrahi +mqsrahi: + set_fr_iimmed 0x0001,0x0002,fr4 + set_fr_iimmed 0x0003,0x0004,fr5 + mqsrahi fr4,#1,fr6 + test_fr_limmed 0x0000,0x0001,fr6 + test_fr_limmed 0x0001,0x0002,fr7 + + set_fr_iimmed 0xffff,0xfffe,fr4 + set_fr_iimmed 0xfffc,0xfff8,fr5 + mqsrahi fr4,#1,fr6 + test_fr_limmed 0xffff,0xffff,fr6 + test_fr_limmed 0xfffe,0xfffc,fr7 + + set_fr_iimmed 0x8000,0xc000,fr4 + set_fr_iimmed 0xe000,0xf000,fr5 + mqsrahi fr4,#12,fr6 + test_fr_limmed 0xfff8,0xfffc,fr6 + test_fr_limmed 0xfffe,0xffff,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsrahi fr4,#12,fr6 + test_fr_limmed 0x0001,0x0005,fr6 + test_fr_limmed 0xfff9,0xfffd,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsrahi fr4,#16,fr6 + test_fr_limmed 0x1234,0x5678,fr6 + test_fr_limmed 0x9abc,0xdef0,fr7 + + pass |