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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-08-31 01:46:08 +0000 |
|---|---|---|
| committer | Andrew Burgess <aburgess@redhat.com> | 2022-10-11 12:38:36 +0100 |
| commit | c6422d7be70f14bf7140085f2fc7a592737f5df5 (patch) | |
| tree | 689a30410844160256c47c3ef26542026ff39fa8 /sim | |
| parent | 029b1ee8d8805ba8cbc4481c107c8e5f32b48eab (diff) | |
| download | gdb-c6422d7be70f14bf7140085f2fc7a592737f5df5.zip gdb-c6422d7be70f14bf7140085f2fc7a592737f5df5.tar.gz gdb-c6422d7be70f14bf7140085f2fc7a592737f5df5.tar.bz2 | |
sim/riscv: fix multiply instructions on simulator
After this commit:
commit 0938b032daa52129b4215d8e0eedb6c9804f5280
Date: Wed Feb 2 10:06:15 2022 +0900
RISC-V: Add 'Zmmul' extension in assembler.
some instructions in the RISC-V simulator stopped working as a new
instruction class 'INSN_CLASS_ZMMUL' was added, and some existing
instructions were moved into this class.
The simulator doesn't currently handle this instruction class, and so
the instructions will now cause an illegal instruction trap.
This commit adds support for INSN_CLASS_ZMMUL, and adds a test that
ensures the affected instructions can be executed by the simulator.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Andrew Burgess <aburgess@redhat.com>
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/riscv/sim-main.c | 1 | ||||
| -rw-r--r-- | sim/testsuite/riscv/m-ext.s | 18 |
2 files changed, 19 insertions, 0 deletions
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 30d2f1e..0156f79 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case INSN_CLASS_I: return execute_i (cpu, iw, op); case INSN_CLASS_M: + case INSN_CLASS_ZMMUL: return execute_m (cpu, iw, op); default: TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class); diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s new file mode 100644 index 0000000..b80bd14 --- /dev/null +++ b/sim/testsuite/riscv/m-ext.s @@ -0,0 +1,18 @@ +# Check that the RV32M instructions run without any faults. +# mach: riscv + +.include "testutils.inc" + + start + + .option arch, +m + mul x0, x1, x2 + mulh x0, x1, x2 + mulhu x0, x1, x2 + mulhsu x0, x1, x2 + div x0, x1, x2 + divu x0, x1, x2 + rem x0, x1, x2 + remu x0, x1, x2 + + pass |