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authorJeff Law <law@redhat.com>1996-08-30 16:35:10 +0000
committerJeff Law <law@redhat.com>1996-08-30 16:35:10 +0000
commit83fc3bac9fd75bd785cf0016ca429b301c30fabd (patch)
treef91c87d77641e63480d36b44dd479dc30282a995 /sim
parent76a61985c130464e743adb6369ccfb1753c090a4 (diff)
downloadgdb-83fc3bac9fd75bd785cf0016ca429b301c30fabd.zip
gdb-83fc3bac9fd75bd785cf0016ca429b301c30fabd.tar.gz
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* interp.c (hash): Fix.
* interp.c (do_format_8): Get operands correctly and call the target function. * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
Diffstat (limited to 'sim')
-rw-r--r--sim/v850/ChangeLog7
-rw-r--r--sim/v850/interp.c37
-rw-r--r--sim/v850/simops.c54
3 files changed, 80 insertions, 18 deletions
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index eb1e528..8c1cbbf 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,10 @@
+Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c (hash): Fix.
+ * interp.c (do_format_8): Get operands correctly and
+ call the target function.
+ * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
+
Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
* interp.c (do_format_4): Get operands correctly and
diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index d47a109..d11c14e 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -27,28 +27,22 @@ static long
hash(insn)
long insn;
{
- if ((insn & 0x30) == 0
- || (insn & 0x38) == 0x10)
+ if ((insn & 0x0600) == 0
+ || (insn & 0x0700) == 0x0200)
return (insn & 0x07e0) >> 5;
- if ((insn & 0x3c) == 0x18
- || (insn & 0x3c) == 0x1c
- || (insn & 0x3c) == 0x20
- || (insn & 0x3c) == 0x24
- || (insn & 0x3c) == 0x28
- || (insn & 0x3c) == 0x23)
- return (insn & 0x07c0) >> 6;
- if ((insn & 0x38) == 0x30)
+ if ((insn & 0x0700) == 0x0300
+ || (insn & 0x0700) == 0x0400
+ || (insn & 0x0700) == 0x0500)
+ return (insn & 0x0780) >> 7;
+ if ((insn & 0x0700) == 0x0600)
return (insn & 0x07e0) >> 5;
- /* What about sub-op field? XXX */
- if ((insn & 0x38) == 0x38)
+ if ((insn & 0x0780) == 0x0700)
return (insn & 0x07e0) >> 5;
- if ((insn & 0x3e) == 0x3c)
+ if ((insn & 0x07c0) == 0x0780)
return (insn & 0x07c0) >> 6;
- if ((insn & 0x3f) == 0x3e)
- return (insn & 0xc7e0) >> 5;
- /* Not really correct. XXX */
- return insn & 0xffffffff;
-
+ if ((insn & 0x07E0) == 0x07C0)
+ return (insn & 0x07e0) >> 5;
+ return (insn & 0x07e0) >> 5;
}
static struct hash_entry *
@@ -208,7 +202,14 @@ static void
do_format_8 (insn)
uint32 insn;
{
+ struct hash_entry *h;
printf("format 8 0x%x\n", insn);
+
+ h = lookup_hash (insn);
+ OP[0] = insn & 0x1f;
+ OP[1] = (insn >> 11) & 0x7;
+ OP[2] = (insn >> 16) & 0xffff;
+ (h->ops->func) ();
}
static void
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index f763d02..1586b11 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -1306,24 +1306,78 @@ OP_20 ()
void
OP_7C0 ()
{
+ unsigned int op0, op1, op2;
+ int result, temp;
+
+ op0 = State.regs[OP[0]];
+ op1 = OP[1] & 0x7;
+ temp = OP[2];
+ temp = (temp << 16) >> 16;
+ op2 = temp;
+ temp = get_byte (State.mem + op0 + op2);
+ State.sregs[5] &= ~PSW_Z;
+ if ((temp & (1 << op1)) == 0)
+ State.sregs[5] |= PSW_Z;
+ temp |= ~(1 << op1);
+ put_byte (State.mem + op0 + op2, temp);
}
/* not1 */
void
OP_47C0 ()
{
+ unsigned int op0, op1, op2;
+ int result, temp;
+
+ op0 = State.regs[OP[0]];
+ op1 = OP[1] & 0x7;
+ temp = OP[2];
+ temp = (temp << 16) >> 16;
+ op2 = temp;
+ temp = get_byte (State.mem + op0 + op2);
+ State.sregs[5] &= ~PSW_Z;
+ if ((temp & (1 << op1)) == 0)
+ State.sregs[5] |= PSW_Z;
+ temp ^= ~(1 << op1);
+ put_byte (State.mem + op0 + op2, temp);
}
/* clr1 */
void
OP_87C0 ()
{
+ unsigned int op0, op1, op2;
+ int result, temp;
+
+ op0 = State.regs[OP[0]];
+ op1 = OP[1] & 0x7;
+ temp = OP[2];
+ temp = (temp << 16) >> 16;
+ op2 = temp;
+ temp = get_byte (State.mem + op0 + op2);
+ State.sregs[5] &= ~PSW_Z;
+ if ((temp & (1 << op1)) == 0)
+ State.sregs[5] |= PSW_Z;
+ temp &= ~(1 << op1);
+ put_byte (State.mem + op0 + op2, temp);
}
/* tst1 */
void
OP_C7C0 ()
{
+ unsigned int op0, op1, op2;
+ int result, temp;
+
+ op0 = State.regs[OP[0]];
+ op1 = OP[1] & 0x7;
+ temp = OP[2];
+ temp = (temp << 16) >> 16;
+ op2 = temp;
+ temp = get_byte (State.mem + op0 + op2);
+ State.sregs[5] &= ~PSW_Z;
+ if ((temp & (1 << op1)) == 0)
+ State.sregs[5] |= PSW_Z;
}
/* di */