diff options
| author | Jeff Law <law@redhat.com> | 1996-08-29 22:29:41 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1996-08-29 22:29:41 +0000 |
| commit | 775533747d0f5d6d1aacfa80cacc7bcbd663b2d1 (patch) | |
| tree | 1cb93fe5d522897b0606e824ab80e5be3458d524 /sim | |
| parent | fb8eb42bd6eff8642f9aa9f3300bc2659b41634e (diff) | |
| download | gdb-775533747d0f5d6d1aacfa80cacc7bcbd663b2d1.zip gdb-775533747d0f5d6d1aacfa80cacc7bcbd663b2d1.tar.gz gdb-775533747d0f5d6d1aacfa80cacc7bcbd663b2d1.tar.bz2 | |
* simops.c: Add shift support.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/v850/ChangeLog | 2 | ||||
| -rw-r--r-- | sim/v850/simops.c | 76 |
2 files changed, 56 insertions, 22 deletions
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog index 546b2bd..af16356 100644 --- a/sim/v850/ChangeLog +++ b/sim/v850/ChangeLog @@ -1,5 +1,7 @@ Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com) + * simops.c: Add shift support. + * simops.c: Add multiply & divide support. Abort for system instructions. diff --git a/sim/v850/simops.c b/sim/v850/simops.c index a6c4768..8ec7871 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -3,11 +3,6 @@ #include "simops.h" void -OP_280 () -{ -} - -void OP_220 () { } @@ -228,16 +223,6 @@ OP_40 () } void -OP_8007E0 () -{ -} - -void -OP_C007E0 () -{ -} - -void OP_10720 () { } @@ -258,11 +243,6 @@ OP_60 () } void -OP_2A0 () -{ -} - -void OP_87C0 () { } @@ -356,19 +336,71 @@ OP_20 () State.regs[OP[1]] = ~State.regs[OP[0]]; } +/* sar zero_extend(imm5),reg1 + + XXX condition codes. */ void -OP_A007E0 () +OP_2A0 () { + int temp = State.regs[OP[1]]; + + temp >>= (OP[0] & 0x1f); + + State.regs[OP[1]] = temp; } +/* sar reg1, reg2 + + XXX condition codes. */ void -OP_500 () +OP_A007E0 () { + int temp = State.regs[OP[1]]; + + temp >>= (State.regs[OP[0]] & 0x1f); + + State.regs[OP[1]] = temp; } +/* shl zero_extend(imm5),reg1 + + XXX condition codes. */ void OP_2C0 () { + State.regs[OP[1]] <<= (OP[0] & 0x1f); +} + +/* shl reg1, reg2 + + XXX condition codes. */ +void +OP_C007E0 () +{ + State.regs[OP[1]] <<= (State.regs[OP[0]] & 0x1f); +} + +/* shr zero_extend(imm5),reg1 + + XXX condition codes. */ +void +OP_280 () +{ + State.regs[OP[1]] >>= (OP[0] & 0x1f); +} + +/* shr reg1, reg2 + + XXX condition codes. */ +void +OP_8007E0 () +{ + State.regs[OP[1]] >>= (State.regs[OP[0]] & 0x1f); +} + +void +OP_500 () +{ } void |