Smooth some of ALU tracing's rough edges.

Fix switch insn.

5 files changed, 292 insertions, 277 deletions

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 1320ab3..1b1b2b5 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,39 @@
+Tue Sep 16 22:14:01 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* simops.c (trace_output): Add result argument.
+	(trace_result): New function.  Simpler version of trace_output,
+ 	assumes trace needed.
+	(trace_output): Call trace_result.
+	(trace_output): For IMM_REG_REG, trace correct register.
+	(trace_input): Add case for 16bit immediates.
+	(OP_600, OP_640, OP_680, OP_6C0, OP_6A0): Use.
+
+	* sim-main.h (TRACE_ALU_INPUT, TRACE_ALU_RESULT): Define.
+	(trace_values, trace_name, trace_pc, trace_num_values): Make
+ 	global.
+	(GR, SR): Define.
+	
+	v850.insn (movea, stsr): Use.
+start-sanitize-v850e
+	(sxb, sxh, zxb, zxh): Ditto.
+end-sanitize-v850e
+	
+Tue Sep 16 21:14:01 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* simops.c: Move "movea" from here.
+	* v850.igen: To here.
+
+	* v850.igen (simm16): Define, sign extend imm16.
+	(uimm16): Define, no sign extension.
+	(addi, andi, movea, movhi, mulhi, ori, satsubi, xori): Use.
+	
+start-sanitize-v850e
+	* simops.c: Move "sxh", "switch", "sxb", "callt", "dispose",
+ 	"mov32" from here.
+	* v850.igen: To here.
+	(switch): Fix off by two error in NIA calc.
+	
+end-sanitize-v850e
 Tue Sep 16 15:14:01 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* simops.c (trace_pc, trace_name, trace_values, trace_num_values):
diff --git a/sim/v850/Makefile.in b/sim/v850/Makefile.in
index 8100e8b..043aa2a 100644
--- a/sim/v850/Makefile.in
+++ b/sim/v850/Makefile.in
@@ -108,7 +108,7 @@ clean-igen:
 ../igen/igen:
 	cd ../igen && $(MAKE)
 
-IGEN_TRACE= -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
+IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
 IGEN_INSN=$(srcdir)/v850.igen
 IGEN_DC=$(srcdir)/v850-dc
 tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index f7222a1..ef70418 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -84,16 +84,16 @@ extern SIM_DESC simulator;
 
 #define SIG_V850_EXIT	-1	/* indication of a normal exit */
 
-extern uint32 OP[4];
 
 /* Because we are still using the old semantic table, provide compat
    macro's that store the instruction where the old simops expects
    it. */
 
+extern uint32 OP[4];
 #if 0
 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
-OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 */
+OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
 OP[3] = inst;
 #endif
 
@@ -122,10 +122,11 @@ PC += (CALL); \
 nia = PC
 
 
-#if 0
-extern struct simops Simops[];
-#endif
+/* new */
+#define GR  ((CPU)->reg.regs)
+#define SR  ((CPU)->reg.sregs)
 
+/* old */
 #define State    (STATE_CPU (simulator, 0)->reg)
 #define PC	(State.pc)
 #define SP	(State.regs[3])
@@ -245,6 +246,8 @@ enum op_types
   OP_JUMP,
   OP_IMM_REG_REG,
   OP_UIMM_REG_REG,
+  OP_IMM16_REG_REG,
+  OP_UIMM16_REG_REG,
   OP_BIT,
   OP_EX1,
   OP_EX2,
@@ -266,9 +269,60 @@ enum op_types
 #ifdef DEBUG
 void trace_input PARAMS ((char *name, enum op_types type, int size));
 void trace_output PARAMS ((enum op_types result));
+void trace_result PARAMS ((int has_result, unsigned32 result));
+
+extern int trace_num_values;
+extern unsigned32 trace_values[];
+extern unsigned32 trace_pc;
+extern const char *trace_name;
+
+#define TRACE_ALU_INPUT0() \
+do { \
+  if (TRACE_ALU_P (CPU)) { \
+    trace_pc = CIA; \
+    trace_name = itable[MY_INDEX].name; \
+    trace_num_values = 0; \
+  } \
+} while (0)
+
+#define TRACE_ALU_INPUT1(IN1) \
+do { \
+  if (TRACE_ALU_P (CPU)) { \
+    trace_pc = CIA; \
+    trace_name = itable[MY_INDEX].name; \
+    trace_values[0] = (IN1); \
+    trace_num_values = 1; \
+  } \
+} while (0)
+
+#define TRACE_ALU_INPUT2(IN1, IN2) \
+do { \
+  if (TRACE_ALU_P (CPU)) { \
+    trace_pc = CIA; \
+    trace_name = itable[MY_INDEX].name; \
+    trace_values[0] = (IN1); \
+    trace_values[1] = (IN2); \
+    trace_num_values = 2; \
+  } \
+} while (0)
+
+#define TRACE_ALU_RESULT(RESULT) \
+do { \
+  if (TRACE_ALU_P (CPU)) { \
+    trace_result (1, (RESULT)); \
+  } \
+} while (0)
+
+
 #else
 #define trace_input(NAME, IN1, IN2)
 #define trace_output(RESULT)
+#define trace_result(HAS_RESULT, RESULT)
+
+#define TRACE_ALU_INPUT0()
+#define TRACE_ALU_INPUT1(IN1)
+#define TRACE_ALU_INPUT2(IN1, IN2)
+#define TRACE_ALU_RESULT(RESULT)
 #endif
 
 
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 583d1a5..4b4bd46 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -64,10 +64,10 @@ int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
 #endif
 
 
-static unsigned32 trace_values[3];
-static int trace_num_values;
-static unsigned32 trace_pc;
-static char *trace_name;
+unsigned32 trace_values[3];
+int trace_num_values;
+unsigned32 trace_pc;
+const char *trace_name;
 
 
 void
@@ -165,12 +165,24 @@ trace_input (name, type, size)
       trace_num_values = 2;
       break;
       
+    case OP_IMM16_REG_REG:
+      trace_values[0] = EXTEND16 (OP[2]) << size;
+      trace_values[1] = State.regs[OP[1]];
+      trace_num_values = 2;
+      break;
+      
     case OP_UIMM_REG_REG:
       trace_values[0] = (OP[0] & 0xffff) << size;
       trace_values[1] = State.regs[OP[1]];
       trace_num_values = 2;
       break;
       
+    case OP_UIMM16_REG_REG:
+      trace_values[0] = (OP[2]) << size;
+      trace_values[1] = State.regs[OP[1]];
+      trace_num_values = 2;
+      break;
+      
     case OP_BIT:
       trace_num_values = 0;
       break;
@@ -197,15 +209,11 @@ trace_input (name, type, size)
 }
 
 void
-trace_output (result)
-     enum op_types result;
+trace_result (int has_result, unsigned32 result)
 {
   char buf[1000];
   char *chp;
 
-  if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
-    return;
-
   buf[0] = '\0';
   chp = buf;
 
@@ -224,6 +232,23 @@ trace_output (result)
       }
   }
 
+  /* append any result to the end of the buffer */
+  if (has_result)
+    sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
+  
+  trace_one_insn (simulator, STATE_CPU (simulator, 0), trace_pc,
+		  TRACE_LINENUM_P (STATE_CPU (simulator, 0)),
+		  "simops", __LINE__, "alu", 
+		  "%-*s -%s", SIZE_INSTRUCTION, trace_name, buf);
+}
+
+void
+trace_output (result)
+     enum op_types result;
+{
+  if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
+    return;
+
   switch (result)
     {
     default:
@@ -238,11 +263,12 @@ trace_output (result)
     case OP_STORE32:
     case OP_BIT:
     case OP_EX2:
+      trace_result (0, 0);
       break;
       
     case OP_LOAD16:
     case OP_STSR:
-      sprintf (chp, " :: 0x%.8lx", (unsigned long)State.regs[OP[0]]);
+      trace_result (1, State.regs[OP[0]]);
       break;
       
     case OP_REG_REG:
@@ -251,29 +277,27 @@ trace_output (result)
     case OP_IMM_REG_MOVE:
     case OP_LOAD32:
     case OP_EX1:
-      sprintf (chp, " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
+      trace_result (1, State.regs[OP[1]]);
       break;
       
     case OP_IMM_REG_REG:
     case OP_UIMM_REG_REG:
-      sprintf (chp, " :: 0x%.8lx", (unsigned long)State.regs[OP[2]]);
+    case OP_IMM16_REG_REG:
+    case OP_UIMM16_REG_REG:
+      trace_result (1, State.regs[OP[1]]);
       break;
       
     case OP_JUMP:
       if (OP[1] != 0)
-	sprintf (chp, " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
+	trace_result (1, State.regs[OP[1]]);
+      else
+	trace_result (0, 0);
       break;
       
     case OP_LDSR:
-      sprintf (chp, " :: 0x%.8lx", (unsigned long)State.sregs[OP[1]]);
+      trace_result (1, State.sregs[OP[1]]);
       break;
     }
-  
-  trace_one_insn (simulator, STATE_CPU (simulator, 0), trace_pc,
-		  TRACE_LINENUM_P (STATE_CPU (simulator, 0)),
-		  "simops", __LINE__, "alu", 
-		  "%-*s -%s", SIZE_INSTRUCTION, trace_name, buf);
-
 }
 #endif
 
@@ -849,7 +873,7 @@ OP_600 ()
 {
   unsigned int op0, op1, result, z, s, cy, ov;
 
-  trace_input ("addi", OP_IMM_REG_REG, 0);
+  trace_input ("addi", OP_IMM16_REG_REG, 0);
 
   /* Compute the result.  */
 
@@ -869,7 +893,7 @@ OP_600 ()
   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
   PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 		| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
-  trace_output (OP_IMM_REG_REG);
+  trace_output (OP_IMM16_REG_REG);
 
   return 4;
 }
@@ -933,28 +957,14 @@ OP_180 ()
 }
 
 /* sxh reg1 */
-/* mulh reg1, reg2 */
 int
 OP_E0 ()
 {
-/* start-sanitize-v850e */
-  if (OP[1] == 0)
-    {
-      trace_input ("sxh", OP_REG, 0);
+  trace_input ("mulh", OP_REG_REG, 0);
       
-      State.regs[ OP[0] ] = EXTEND16 (State.regs[ OP[0] ]);
-
-      trace_output (OP_REG);
-    }
-  else
-/* end-sanitize-v850e */
-    {
-      trace_input ("mulh", OP_REG_REG, 0);
-      
-      State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
+  State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
       
-      trace_output (OP_REG_REG);
-    }
+  trace_output (OP_REG_REG);
 
   return 2;
 }
@@ -976,72 +986,55 @@ OP_2E0 ()
 int
 OP_6E0 ()
 {
-  trace_input ("mulhi", OP_IMM_REG_REG, 0);
+  trace_input ("mulhi", OP_IMM16_REG_REG, 0);
   
   State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
       
-  trace_output (OP_IMM_REG_REG);
+  trace_output (OP_IMM16_REG_REG);
   
   return 4;
 }
 
 /* divh reg1, reg2 */
-/* switch  reg1 */
 int
 OP_40 ()
 {
-/* start-sanitize-v850e */
-  if (OP[1] == 0)
-    {
-      unsigned long adr;
+  unsigned int op0, op1, result, ov, s, z;
+  int temp;
 
-      trace_input ("switch", OP_REG, 0);
-      
-      adr      = State.pc + 2 + (State.regs[ OP[0] ] << 1);
-      State.pc = State.pc + 2 + (EXTEND16 (load_mem (adr, 2)) << 1);
+  trace_input ("divh", OP_REG_REG, 0);
 
-      trace_output (OP_REG);
+  /* Compute the result.  */
+  temp = EXTEND16 (State.regs[ OP[0] ]);
+  op0 = temp;
+  op1 = State.regs[OP[1]];
+  
+  if (op0 == 0xffffffff && op1 == 0x80000000)
+    {
+      result = 0x80000000;
+      ov = 1;
+    }
+  else if (op0 != 0)
+    {
+      result = op1 / op0;
+      ov = 0;
     }
   else
-/* end-sanitize-v850e */
     {
-      unsigned int op0, op1, result, ov, s, z;
-      int temp;
-
-      trace_input ("divh", OP_REG_REG, 0);
-
-      /* Compute the result.  */
-      temp = EXTEND16 (State.regs[ OP[0] ]);
-      op0 = temp;
-      op1 = State.regs[OP[1]];
-      
-      if (op0 == 0xffffffff && op1 == 0x80000000)
-	{
-	  result = 0x80000000;
-	  ov = 1;
-	}
-      else if (op0 != 0)
-	{
-	  result = op1 / op0;
-	  ov = 0;
-	}
-      else
-	{
-	  result = 0x0;
-	  ov = 1;
-	}
-      
-      /* Compute the condition codes.  */
-      z = (result == 0);
-      s = (result & 0x80000000);
-      
-      /* Store the result and condition codes.  */
-      State.regs[OP[1]] = result;
-      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-      PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
-	      | (ov ? PSW_OV : 0));
-      trace_output (OP_REG_REG);
+      result = 0x0;
+      ov = 1;
     }
+  
+  /* Compute the condition codes.  */
+  z = (result == 0);
+  s = (result & 0x80000000);
+  
+  /* Store the result and condition codes.  */
+  State.regs[OP[1]] = result;
+  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
+	  | (ov ? PSW_OV : 0));
+  trace_output (OP_REG_REG);
 
   return 2;
 }
@@ -1196,54 +1189,39 @@ OP_220 ()
 }
 
 /* satsub reg1, reg2 */
-/* sxb reg1 */
 int
 OP_A0 ()
 {
-/* start-sanitize-v850e */
-  if (OP[1] == 0)
-    {
-      trace_input ("sxb", OP_REG, 0);
-
-      State.regs[ OP[0] ] = EXTEND8 (State.regs[ OP[0] ]);
-
-      trace_output (OP_REG);
-    }
-  else
-/* end-sanitize-v850e */
-    {
-      unsigned int op0, op1, result, z, s, cy, ov, sat;
-
-      trace_input ("satsub", OP_REG_REG, 0);
-      
-      /* Compute the result.  */
-      op0 = State.regs[ OP[0] ];
-      op1 = State.regs[ OP[1] ];
-      result = op1 - op0;
-      
-      /* Compute the condition codes.  */
-      z = (result == 0);
-      s = (result & 0x80000000);
-      cy = (op1 < op0);
-      ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
-	    && (op1 & 0x80000000) != (result & 0x80000000));
-      sat = ov;
-      
-      /* Store the result and condition codes.  */
-      State.regs[OP[1]] = result;
-      PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
-      PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
-	      | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
-	      | (sat ? PSW_SAT : 0));
-      
-      /* Handle saturated results.  */
-      if (sat && s)
-	State.regs[OP[1]] = 0x80000000;
-      else if (sat)
-	State.regs[OP[1]] = 0x7fffffff;
-      trace_output (OP_REG_REG);
-    }
-
+  unsigned int op0, op1, result, z, s, cy, ov, sat;
+  
+  trace_input ("satsub", OP_REG_REG, 0);
+  
+  /* Compute the result.  */
+  op0 = State.regs[ OP[0] ];
+  op1 = State.regs[ OP[1] ];
+  result = op1 - op0;
+  
+  /* Compute the condition codes.  */
+  z = (result == 0);
+  s = (result & 0x80000000);
+  cy = (op1 < op0);
+  ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
+	&& (op1 & 0x80000000) != (result & 0x80000000));
+  sat = ov;
+  
+  /* Store the result and condition codes.  */
+  State.regs[OP[1]] = result;
+  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
+	  | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
+	  | (sat ? PSW_SAT : 0));
+  
+  /* Handle saturated results.  */
+  if (sat && s)
+    State.regs[OP[1]] = 0x80000000;
+  else if (sat)
+    State.regs[OP[1]] = 0x7fffffff;
+  trace_output (OP_REG_REG);
   return 2;
 }
 
@@ -1364,112 +1342,29 @@ OP_0 ()
 }
 
 /* mov sign_extend(imm5), reg */
-/* callt imm6 */
 int
 OP_200 ()
 {
-/* start-sanitize-v850e */
-  if (OP[1] == 0)
-    {
-      unsigned long adr;
-      
-      trace_input ("callt", OP_LOAD16, 1);
-      
-      CTPC  = PC + 2;
-      CTPSW = PSW;
-      
-      adr = CTBP + ((OP[3] & 0x3f) << 1);
-      
-      PC = CTBP + load_mem (adr, 1);
-
-      trace_output (OP_LOAD16);
-
-      return 0;
-    }
-  else
-/* end-sanitize-v850e */
-    {
-      int value = SEXT5 (OP[0]);
- 
-      trace_input ("mov", OP_IMM_REG_MOVE, 0);
-      
-      State.regs[ OP[1] ] = value;
-      
-      trace_output (OP_IMM_REG_MOVE);
-
-      return 2;
-    }
-}
-
-/* mov imm32, reg1 */
-/* movea sign_extend(imm16), reg, reg  */
-int
-OP_620 ()
-{
-/* start-sanitize-v850e */
-  if (OP[1] == 0)
-    {
-      trace_input ("mov", OP_IMM_REG, 4);
-
-      State.regs[ OP[0] ] = load_mem (PC + 2, 4);
-      
-      trace_output (OP_IMM_REG);
-
-      return 6;
-    }
-  else
-/* end-sanitize-v850e */
-    {
-      trace_input ("movea", OP_IMM_REG_REG, 0);
+  int value = SEXT5 (OP[0]);
   
-      State.regs[ OP[1] ] = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
+  trace_input ("mov", OP_IMM_REG_MOVE, 0);
   
-      trace_output (OP_IMM_REG_REG);
-
-      return 4;
-    }
+  State.regs[ OP[1] ] = value;
+  
+  trace_output (OP_IMM_REG_MOVE);
+  
+  return 2;
 }
 
-/* dispose imm5, list12 [, reg1] */
 /* movhi imm16, reg, reg */
 int
 OP_640 ()
 {
-/* start-sanitize-v850e */
-
-  if (OP[1] == 0)
-    {
-      int        i;
-      
-      trace_input ("dispose", OP_PUSHPOP1, 0);
-
-      SP += (OP[3] & 0x3e) << 1;
-
-      /* Load the registers with lower number registers being retrieved from higher addresses.  */
-      for (i = 12; i--;)
-	if ((OP[3] & (1 << type1_regs[ i ])))
-	  {
-	    State.regs[ 20 + i ] = load_mem (SP, 4);
-	    SP += 4;
-	  }
-
-      if ((OP[3] & 0x1f0000) != 0)
-	{
-	  PC = State.regs[ (OP[3] >> 16) & 0x1f];
-	  return 0;
-	}
+  trace_input ("movhi", OP_UIMM16_REG_REG, 16);
       
-      trace_output (OP_PUSHPOP1);
-    }
-  else
-/* end-sanitize-v850e */
-    {
-      trace_input ("movhi", OP_UIMM_REG_REG, 16);
+  State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
       
-      State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
-      
-      trace_output (OP_UIMM_REG_REG);
-    }
+  trace_output (OP_UIMM16_REG_REG);
 
   return 4;
 }
@@ -1663,7 +1558,7 @@ OP_680 ()
 {
   unsigned int op0, op1, result, z, s;
 
-  trace_input ("ori", OP_UIMM_REG_REG, 0);
+  trace_input ("ori", OP_UIMM16_REG_REG, 0);
   op0 = OP[2];
   op1 = State.regs[ OP[0] ];
   result = op0 | op1;
@@ -1676,7 +1571,7 @@ OP_680 ()
   State.regs[OP[1]] = result;
   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
-  trace_output (OP_UIMM_REG_REG);
+  trace_output (OP_UIMM16_REG_REG);
 
   return 4;
 }
@@ -1713,7 +1608,7 @@ OP_6C0 ()
 {
   unsigned int result, z;
 
-  trace_input ("andi", OP_UIMM_REG_REG, 0);
+  trace_input ("andi", OP_UIMM16_REG_REG, 0);
 
   result = OP[2] & State.regs[ OP[0] ];
 
@@ -1726,7 +1621,7 @@ OP_6C0 ()
   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   PSW |= (z ? PSW_Z : 0);
   
-  trace_output (OP_UIMM_REG_REG);
+  trace_output (OP_UIMM16_REG_REG);
 
   return 4;
 }
@@ -1763,7 +1658,7 @@ OP_6A0 ()
 {
   unsigned int op0, op1, result, z, s;
 
-  trace_input ("xori", OP_UIMM_REG_REG, 0);
+  trace_input ("xori", OP_UIMM16_REG_REG, 0);
   op0 = OP[2];
   op1 = State.regs[ OP[0] ];
   result = op0 ^ op1;
@@ -1776,7 +1671,7 @@ OP_6A0 ()
   State.regs[OP[1]] = result;
   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
-  trace_output (OP_UIMM_REG_REG);
+  trace_output (OP_UIMM16_REG_REG);
 
   return 4;
 }
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index e1f8556..f9b46ac 100644
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -52,10 +52,10 @@
 # start-sanitize-v850eq
 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
 # end-sanitize-v850eq
-:cache::unsigned:imm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
+:cache::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
+:cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
 # start-sanitize-v850e
-:cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
 # end-sanitize-v850e
 
@@ -97,7 +97,7 @@ rrrrr,010010,iiiii:II:::add
 
 // ADDI
 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
-"addi <imm16>, r<reg1>, r<reg2>"
+"addi <simm16>, r<reg1>, r<reg2>"
 {
   COMPAT_2 (OP_600 ());
 }
@@ -115,7 +115,7 @@ rrrrr,001010,RRRRR:I:::and
 
 // ANDI
 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
-"andi <imm16>, r<reg1>, r<reg2>"
+"andi <uimm16>, r<reg1>, r<reg2>"
 {
   COMPAT_2 (OP_6C0 ());
 }
@@ -263,7 +263,14 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 // end-sanitize-v850eq
 "callt <imm6>"
 {
-  COMPAT_1 (OP_200 ());
+  unsigned long adr;
+  SAVE_1;
+  trace_input ("callt", OP_LOAD16, 1);
+  CTPC  = cia + 2;
+  CTPSW = PSW;
+  adr = CTBP + ((OP[3] & 0x3f) << 1);
+  nia = CTBP + load_mem (adr, 1);
+  trace_output (OP_LOAD16);
 }
 
 
@@ -368,7 +375,28 @@ rrrrr,010011,iiiii:II:::cmp
 "dispose <imm5>, <list12>":RRRRR == 0
 "dispose <imm5>, <list12>, [reg1]"
 {
-  COMPAT_2 (OP_640 ());
+  int i;
+  SAVE_2;
+      
+  trace_input ("dispose", OP_PUSHPOP1, 0);
+
+  SP += (OP[3] & 0x3e) << 1;
+
+  /* Load the registers with lower number registers being retrieved
+     from higher addresses.  */
+  for (i = 12; i--;)
+    if ((OP[3] & (1 << type1_regs[ i ])))
+      {
+	State.regs[ 20 + i ] = load_mem (SP, 4);
+	SP += 4;
+      }
+  
+  if ((OP[3] & 0x1f0000) != 0)
+    {
+      nia = State.regs[ (OP[3] >> 16) & 0x1f];
+    }
+  
+  trace_output (OP_PUSHPOP1);
 }
 
 
@@ -579,7 +607,10 @@ rrrrr!0,010000,iiiii:II:::mov
 // end-sanitize-v850eq
 "mov <imm32>, r<reg1>"
 {
-  COMPAT_2 (OP_620 ());
+  SAVE_2;
+  trace_input ("mov", OP_IMM_REG, 4);
+  State.regs[ OP[0] ] = load_mem (PC + 2, 4);
+  trace_output (OP_IMM_REG);
 }
 
 
@@ -587,16 +618,18 @@ rrrrr!0,010000,iiiii:II:::mov
 // end-sanitize-v850e
 // MOVEA
 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
-"movea <imm16>, r<reg1>, r<reg2>"
+"movea <simm16>, r<reg1>, r<reg2>"
 {
-  COMPAT_2 (OP_620 ());
+  TRACE_ALU_INPUT2 (GR[reg1], simm16);
+  GR[reg2] = GR[reg1] + simm16;
+  TRACE_ALU_RESULT (GR[reg2]);
 }
 
 
 
 // MOVHI
 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
-"movhi <imm16>, r<reg1>, r<reg2>"
+"movhi <uimm16>, r<reg1>, r<reg2>"
 {
   COMPAT_2 (OP_640 ());
 }
@@ -647,7 +680,7 @@ rrrrr!0,010111,iiiii:II:::mulh
 
 // MULHI
 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
-"mulhi <imm16>, r<reg1>, r<reg2>"
+"mulhi <uimm16>, r<reg1>, r<reg2>"
 {
   COMPAT_2 (OP_6E0 ());
 }
@@ -729,7 +762,7 @@ rrrrr,001000,RRRRR:I:::or
 
 // ORI 
 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
-"ori <imm16>, r<reg1>, r<reg2>"
+"ori <uimm16>, r<reg1>, r<reg2>"
 {
   COMPAT_2 (OP_680 ());
 }
@@ -874,7 +907,7 @@ rrrrr!0,000101,RRRRR:I:::satsub
 
 // SATSUBI
 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
-"satsubi <imm16>, r<reg1>, r<reg2>"
+"satsubi <simm16>, r<reg1>, r<reg2>"
 {
   COMPAT_2 (OP_660 ());
 }
@@ -1055,13 +1088,9 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
 "stsr r<regID>, r<reg1>"
 {
-  SAVE_2;
-
-  trace_input ("stsr", OP_STSR, 0);
-  
-  State.regs[ reg1 ] = State.sregs[ regID ];
-  
-  trace_output (OP_STSR);
+  TRACE_ALU_INPUT0();
+  GR[reg1] = SR[regID];
+  TRACE_ALU_RESULT (GR[reg1]);
 }
 
 
@@ -1093,12 +1122,17 @@ rrrrr,001100,RRRRR:I:::subr
 // end-sanitize-v850eq
 "switch r<reg1>"
 {
-  COMPAT_1 (OP_40 ());
+  unsigned long adr;
+  SAVE_1;
+  trace_input ("switch", OP_REG, 0);
+  adr = (cia + 2) + (State.regs[ reg1 ] << 1);
+  nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
+  trace_output (OP_REG);
 }
-// end-sanitize-v850e
 
 
 
+// end-sanitize-v850e
 // start-sanitize-v850e
 // SXB
 00000000101,RRRRR:I:::sxb
@@ -1108,7 +1142,9 @@ rrrrr,001100,RRRRR:I:::subr
 // end-sanitize-v850eq
 "sxb r<reg1>"
 {
-  COMPAT_1 (OP_A0 ());
+  TRACE_ALU_INPUT1 (GR[reg1]);
+  GR[reg1] = EXTEND8 (GR[reg1]);
+  TRACE_ALU_RESULT (GR[reg1]);
 }
 
 
@@ -1123,7 +1159,9 @@ rrrrr,001100,RRRRR:I:::subr
 // end-sanitize-v850eq
 "sxh r<reg1>"
 {
-  COMPAT_1 (OP_E0 ());
+  TRACE_ALU_INPUT1 (GR[reg1]);
+  GR[reg1] = EXTEND16 (GR[reg1]);
+  TRACE_ALU_RESULT (GR[reg1]);
 }
 
 
@@ -1179,7 +1217,7 @@ rrrrr,001001,RRRRR:I:::xor
 
 // XORI
 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
-"xori <imm16>, r<reg1>, r<reg2>"
+"xori <uimm16>, r<reg1>, r<reg2>"
 {
   COMPAT_2 (OP_6A0 ());
 }
@@ -1195,13 +1233,9 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 // end-sanitize-v850eq
 "zxb r<reg1>"
 {
-  SAVE_1;
-
-  trace_input ("zxb", OP_REG, 0);
-
-  State.regs[ OP[0] ] &= 0xff;
-
-  trace_output (OP_REG);
+  TRACE_ALU_INPUT1 (GR[reg1]);
+  GR[reg1] = GR[reg1] & 0xff;
+  TRACE_ALU_RESULT (GR[reg1]);
 }
 
 
@@ -1216,13 +1250,9 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 // end-sanitize-v850eq
 "zxh r<reg1>"
 {
-  SAVE_1;
-
-  trace_input ("zxh", OP_REG, 0);
-      
-  State.regs[ OP[0] ] &= 0xffff;
-
-  trace_output (OP_REG);
+  TRACE_ALU_INPUT1 (GR[reg1]);
+  GR[reg1] = GR[reg1] & 0xffff;
+  TRACE_ALU_RESULT (GR[reg1]);
 }