diff options
| author | Andrew Cagney <cagney@redhat.com> | 1997-09-19 00:50:19 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-09-19 00:50:19 +0000 |
| commit | 60fe0e06a825b1e36c35534d53d2196f01a3d74d (patch) | |
| tree | 6e66e7128e00cc54326612eef74cbd8d40e582db /sim/v850 | |
| parent | 46ad7d6ccb1590b1a2fee9c1ab06a5e3f2622921 (diff) | |
| download | gdb-60fe0e06a825b1e36c35534d53d2196f01a3d74d.zip gdb-60fe0e06a825b1e36c35534d53d2196f01a3d74d.tar.gz gdb-60fe0e06a825b1e36c35534d53d2196f01a3d74d.tar.bz2 | |
Fix cmov insn.
Diffstat (limited to 'sim/v850')
| -rw-r--r-- | sim/v850/ChangeLog | 9 | ||||
| -rw-r--r-- | sim/v850/sim-main.h | 17 | ||||
| -rw-r--r-- | sim/v850/simops.c | 17 | ||||
| -rw-r--r-- | sim/v850/v850.igen | 4 |
4 files changed, 30 insertions, 17 deletions
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog index 8787007..6474355 100644 --- a/sim/v850/ChangeLog +++ b/sim/v850/ChangeLog @@ -1,3 +1,12 @@ +Fri Sep 19 10:37:20 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * simops.c (condition_met): Make global. + * sim-main.h (TRACE_ALU_INPUT3): Define. + +start-sanitize-v850e + * simops.c (OP_32007E0): Move "cmov" to v850.igen, fix. + +end-sanitize-v850e Wed Sep 17 16:21:08 1997 Andrew Cagney <cagney@b1.cygnus.com> * simops.c: Move "mov", "reti", to v850.igen, fix tracing. diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h index a4c57af..2d1bf6a 100644 --- a/sim/v850/sim-main.h +++ b/sim/v850/sim-main.h @@ -224,6 +224,10 @@ sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \ PC, sim_core_write_map, (ADDR), (DATA)) +/* compare cccc field against PSW */ +unsigned int condition_met (unsigned code); + + /* Debug/tracing calls */ enum op_types @@ -310,6 +314,19 @@ do { \ } \ } while (0) +#define TRACE_ALU_INPUT3(IN0, IN1, IN2) \ +do { \ + if (TRACE_ALU_P (CPU)) { \ + trace_module = "alu"; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_values[0] = (IN0); \ + trace_values[1] = (IN1); \ + trace_values[2] = (IN2); \ + trace_num_values = 3; \ + } \ +} while (0) + #define TRACE_ALU_RESULT(RESULT) \ do { \ if (TRACE_ALU_P (CPU)) { \ diff --git a/sim/v850/simops.c b/sim/v850/simops.c index 8a360a3..b55b430 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -305,7 +305,7 @@ trace_output (result) /* Returns 1 if the specific condition is met, returns 0 otherwise. */ -static unsigned int +unsigned int condition_met (unsigned code) { unsigned int psw = PSW; @@ -2898,21 +2898,6 @@ OP_70 (void) /* end-sanitize-v850e */ /* start-sanitize-v850e */ -/* cmov reg1, reg2, reg3 */ -int -OP_32007E0 (void) -{ - trace_input ("cmov", OP_REG_REG_REG, 0); - - State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ]; - - trace_output (OP_REG_REG_REG); - - return 4; -} - -/* end-sanitize-v850e */ -/* start-sanitize-v850e */ /* mul reg1, reg2, reg3 */ int OP_22007E0 (void) diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index fd45a30..192a302 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -353,7 +353,9 @@ rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov // end-sanitize-v850eq "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>" { - COMPAT_2 (OP_32007E0 ()); + TRACE_ALU_INPUT3 (cccc, GR[reg1], GR[reg2]); + GR[reg3] = condition_met (cccc) ? GR[reg1] : GR[reg2]; + TRACE_ALU_RESULT (GR[reg3]); } // end-sanitize-v850e |