Clean up tracing for Bcond & jmp insns.

Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.

4 files changed, 162 insertions, 369 deletions

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index cfcf3bb..4c21399 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,8 +1,28 @@
 Fri Sep 19 10:37:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
+	* v850.igen (disp16): Use EXTEND16 to sign extend disp.
+	(disp22): Only shift left by 1, not 2.
+	("jmp"): Ensure PC is 2 byte aligned.
+
+	* simops.c, v850.igen: Move "Bcond", "jr", "jarl" code to
+ 	v850.igen. Fix tracing.
+
+	* simops.c (OP_300, OP_400, OP_500): Move "sdl.b", "sld.h",
+ 	"sld.w" insns to v850.igen.  Fix tracing.
+start-sanitize-v850eq
+	(OP_70): Ditto for "sld.hu".
+end-sanitize-v850eq
+
+	* v850.igen: Clarify tracing of "sld.b", "sld.h" et.al.
+
+end-sanitize-v850eq
 	* simops.c (condition_met): Make global.
 
-	* sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0): Define.
+	* sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0, TRACE_LD,
+ 	TRACE_ST): Define.
+start-sanitize-v850eq
+	(TRACE_LD_NAME): Define.
+end-sanitize-v850eq
 
 start-sanitize-v850e
 	* simops.c: Move "cmov", "cmov imm" to v850.igen, fix.
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index 99b508c..5f08889 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -384,6 +384,43 @@ do { \
   } \
 } while (0)
 
+#define TRACE_LD(ADDR,RESULT) \
+do { \
+  if (TRACE_MEMORY_P (CPU)) { \
+    trace_module = "memory"; \
+    trace_pc = cia; \
+    trace_name = itable[MY_INDEX].name; \
+    trace_values[0] = (ADDR); \
+    trace_num_values = 1; \
+    trace_result (1, (RESULT)); \
+  } \
+} while (0)
+
+/* start-sanitize-v850e */
+#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
+do { \
+  if (TRACE_MEMORY_P (CPU)) { \
+    trace_module = "memory"; \
+    trace_pc = cia; \
+    trace_name = (NAME); \
+    trace_values[0] = (ADDR); \
+    trace_num_values = 1; \
+    trace_result (1, (RESULT)); \
+  } \
+} while (0)
+
+/* end-sanitize-v850e */
+#define TRACE_ST(ADDR,RESULT) \
+do { \
+  if (TRACE_MEMORY_P (CPU)) { \
+    trace_module = "memory"; \
+    trace_pc = cia; \
+    trace_name = itable[MY_INDEX].name; \
+    trace_values[0] = (ADDR); \
+    trace_num_values = 1; \
+    trace_result (1, (RESULT)); \
+  } \
+} while (0)
 
 #else
 #define trace_input(NAME, IN1, IN2)
@@ -401,6 +438,10 @@ do { \
 #define TRACE_BRANCH1(IN1)
 #define TRACE_BRANCH2(IN1, IN2)
 #define TRACE_BRANCH2(IN1, IN2, IN3)
+
+#define TRACE_LD(ADDR,RESULT)
+#define TRACE_ST(ADDR,RESULT)
+
 #endif
 
 
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index c739d60..543ab91 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -455,77 +455,6 @@ fetch_argv (sd, addr)
 }
 
 
-/* sld.b */
-int
-OP_300 ()
-{
-  unsigned long result;
-  
-  result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
-
-/* start-sanitize-v850eq */
-  if (PSW & PSW_US)
-    {
-      trace_input ("sld.bu", OP_LOAD16, 1);
-      State.regs[ OP[1] ] = result;
-    }
-  else
-    {
-/* end-sanitize-v850eq */
-  trace_input ("sld.b", OP_LOAD16, 1);
-  
-  State.regs[ OP[1] ] = EXTEND8 (result);
-/* start-sanitize-v850eq */
-    }
-/* end-sanitize-v850eq */
-  
-  trace_output (OP_LOAD16);
-  
-  return 2;
-}
-
-/* sld.h */
-int
-OP_400 ()
-{
-  unsigned long result;
-  
-  result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
-
-/* start-sanitize-v850eq */
-  if (PSW & PSW_US)
-    {
-      trace_input ("sld.hu", OP_LOAD16, 2);
-      State.regs[ OP[1] ] = result;
-    }
-  else
-    {
-/* end-sanitize-v850eq */
-  trace_input ("sld.h", OP_LOAD16, 2);
-  
-  State.regs[ OP[1] ] = EXTEND16 (result);
-/* start-sanitize-v850eq */
-    }
-/* end-sanitize-v850eq */
-  
-  trace_output (OP_LOAD16);
-
-  return 2;
-}
-
-/* sld.w */
-int
-OP_500 ()
-{
-  trace_input ("sld.w", OP_LOAD16, 4);
-  
-  State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
-  
-  trace_output (OP_LOAD16);
-  
-  return 2;
-}
-
 /* sst.b */
 int
 OP_380 ()
@@ -667,144 +596,6 @@ OP_10760 ()
   return 4;
 }
 
-static int
-branch (int code)
-{
-  trace_input ("Bcond", OP_COND_BR, 0);
-  trace_output (OP_COND_BR);
-
-  if (condition_met (code))
-    return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
-  else
-    return 2;
-}
-
-/* bv disp9 */
-int
-OP_580 ()
-{
-  return branch (0);
-}
-
-/* bl disp9 */
-int
-OP_581 ()
-{
-  return branch (1);
-}
-
-/* be disp9 */
-int
-OP_582 ()
-{
-  return branch (2);
-}
-
-/* bnh disp 9*/
-int
-OP_583 ()
-{
-  return branch (3);
-}
-
-/* bn disp9 */
-int
-OP_584 ()
-{
-  return branch (4);
-}
-
-/* br disp9 */
-int
-OP_585 ()
-{
-  return branch (5);
-}
-
-/* blt disp9 */
-int
-OP_586 ()
-{
-  return branch (6);
-}
-
-/* ble disp9 */
-int
-OP_587 ()
-{
-  return branch (7);
-}
-
-/* bnv disp9 */
-int
-OP_588 ()
-{
-  return branch (8);
-}
-
-/* bnl disp9 */
-int
-OP_589 ()
-{
-  return branch (9);
-}
-
-/* bne disp9 */
-int
-OP_58A ()
-{
-  return branch (10);
-}
-
-/* bh disp9 */
-int
-OP_58B ()
-{
-  return branch (11);
-}
-
-/* bp disp9 */
-int
-OP_58C ()
-{
-  return branch (12);
-}
-
-/* bsa disp9 */
-int
-OP_58D ()
-{
-  return branch (13);
-}
-
-/* bge disp9 */
-int
-OP_58E ()
-{
-  return branch (14);
-}
-
-/* bgt disp9 */
-int
-OP_58F ()
-{
-  return branch (15);
-}
-
-/* jarl/jr disp22, reg */
-int
-OP_780 ()
-{
-  trace_input ("jarl/jr", OP_JUMP, 0);
-
-  if (OP[ 1 ] != 0)
-    State.regs[ OP[1] ] = PC + 4;
-  
-  trace_output (OP_JUMP);
-  
-  return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
-}
-
 /* add reg, reg */
 int
 OP_1C0 ()
@@ -2851,37 +2642,6 @@ OP_30780 (void)
 
 /* end-sanitize-v850e */
 /* start-sanitize-v850e */
-/* sld.hu */
-int
-OP_70 (void)
-{
-  unsigned long result;
-  
-  result  = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
-
-  /* start-sanitize-v850eq */
-  if (PSW & PSW_US)
-    {
-      trace_input ("sld.h", OP_LOAD16, 2);
-      State.regs[ OP[1] ] = EXTEND16 (result);
-    }
-  else
-    {
-/* end-sanitize-v850eq */
-  trace_input ("sld.hu", OP_LOAD16, 2);
-  
-  State.regs[ OP[1] ] = result;
-/* start-sanitize-v850eq */
-    }
-/* end-sanitize-v850eq */
-  
-  trace_output (OP_LOAD16);
-  
-  return 2;
-}
-
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
 /* mul reg1, reg2, reg3 */
 int
 OP_22007E0 (void)
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 5ff2dc5..95103ca 100644
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -40,10 +40,9 @@
 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
 :cache::unsigned:disp8:dddddd:(dddddd << 2)
 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
-:cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
-:cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
-:cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
-:cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
+:cache::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
+:cache::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
+:cache::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
 
 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
 :cache::unsigned:imm6:iiiiii:iiiiii
@@ -158,109 +157,13 @@ rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 
 
 // Bcond
-// ddddd,1011,ddd,cccc:III:::Bcond
-// "b%s<cccc> <disp9>"
-// {
-//   int cond = condition_met (cccc);
-//   if (cond)
-//     nia = cia + disp9;
-//   TRACE_BRANCH1 (cond);
-// }
-
-ddddd,1011,ddd,0000:III:::bv
-"bv <disp9>"
-{
-  COMPAT_1 (OP_580 ());
-}
-
-ddddd,1011,ddd,0001:III:::bl
-"bl <disp9>"
-{
-  COMPAT_1 (OP_581 ());
-}
-
-ddddd,1011,ddd,0010:III:::be
-"be <disp9>"
-{
-  COMPAT_1 (OP_582 ());
-}
-
-ddddd,1011,ddd,0011:III:::bnh
-"bnh <disp9>"
-{
-  COMPAT_1 (OP_583 ());
-}
-
-ddddd,1011,ddd,0100:III:::bn
-"bn <disp9>"
-{
-  COMPAT_1 (OP_584 ());
-}
-
-ddddd,1011,ddd,0101:III:::br
-"br <disp9>"
-{
-  COMPAT_1 (OP_585 ());
-}
-
-ddddd,1011,ddd,0110:III:::blt
-"blt <disp9>"
-{
-  COMPAT_1 (OP_586 ());
-}
-
-ddddd,1011,ddd,0111:III:::ble
-"ble <disp9>"
+ddddd,1011,ddd,cccc:III:::Bcond
+"b%s<cccc> <disp9>"
 {
-  COMPAT_1 (OP_587 ());
-}
-
-ddddd,1011,ddd,1000:III:::bnv
-"bnv <disp9>"
-{
-  COMPAT_1 (OP_588 ());
-}
-
-ddddd,1011,ddd,1001:III:::bnl
-"bnl <disp9>"
-{
-  COMPAT_1 (OP_589 ());
-}
-
-ddddd,1011,ddd,1010:III:::bne
-"bne <disp9>"
-{
-  COMPAT_1 (OP_58A ());
-}
-
-ddddd,1011,ddd,1011:III:::bh
-"bh <disp9>"
-{
-  COMPAT_1 (OP_58B ());
-}
-
-ddddd,1011,ddd,1100:III:::bp
-"bp <disp9>"
-{
-  COMPAT_1 (OP_58C ());
-}
-
-ddddd,1011,ddd,1101:III:::bsa
-"bsa <disp9>"
-{
-  COMPAT_1 (OP_58D ());
-}
-
-ddddd,1011,ddd,1110:III:::bge
-"bge <disp9>"
-{
-  COMPAT_1 (OP_58E ());
-}
-
-ddddd,1011,ddd,1111:III:::bgt
-"bgt <disp9>"
-{
-  COMPAT_1 (OP_58F ());
+  int cond = condition_met (cccc);
+  if (cond)
+    nia = cia + disp9;
+  TRACE_BRANCH1 (cond);
 }
 
 
@@ -589,7 +492,9 @@ rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 "jarl <disp22>, r<reg2>"
 {
-  COMPAT_2 (OP_780 ());
+  GR[reg2] = nia;
+  nia = cia + disp22;
+  TRACE_BRANCH1 (GR[reg2]);
 }
 
 
@@ -598,7 +503,7 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 00000000011,RRRRR:I:::jmp
 "jmp [r<reg1>]"
 {
-  nia = GR[reg1];
+  nia = GR[reg1] & ~1;
   TRACE_BRANCH0 ();
 }
 
@@ -608,14 +513,15 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 "jr <disp22>"
 {
-  COMPAT_2 (OP_780 ());
+  nia = cia + disp22;
+  TRACE_BRANCH0 ();
 }
 
 
 
 // LD
 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
-"ld.b <disp16>[r<reg1>, r<reg2>"
+"ld.b <disp16>[r<reg1>], r<reg2>"
 {
   COMPAT_2 (OP_700 ());
 }
@@ -1090,53 +996,119 @@ rrrrr,010100,iiiii:II:::shr
 
 // SLD
 rrrrr,0110,ddddddd:IV:::sld.b
+// start-sanitize-v850eq
+"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
+// end-sanitize-v850eq
 "sld.b <disp7>[ep], r<reg2>"
 {
-  COMPAT_1 (OP_300 ());
+  unsigned32 addr = EP + disp7;
+  unsigned32 result = load_mem (addr, 1);
+  /* start-sanitize-v850eq */
+  if (PSW & PSW_US)
+    {
+      GR[reg2] = result;
+      TRACE_LD_NAME ("sld.bu", addr, result);
+    }
+  else
+    {
+/* end-sanitize-v850eq */
+  result = EXTEND8 (result);
+  GR[reg2] = result;
+  TRACE_LD (addr, result);
+/* start-sanitize-v850eq */
+    }
+/* end-sanitize-v850eq */
 }
 
 rrrrr,1000,ddddddd:IV:::sld.h
+// start-sanitize-v850eq
+"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
+// end-sanitize-v850eq
 "sld.h <disp8>[ep], r<reg2>"
 {
-  COMPAT_1 (OP_400 ());
+  unsigned32 addr = EP + disp8;
+  unsigned32 result = load_mem (addr, 2);
+  /* start-sanitize-v850eq */
+  if (PSW & PSW_US)
+    {
+      GR[reg2] = result;
+      TRACE_LD_NAME ("sld.hu", addr, result);
+    }
+  else
+    {
+/* end-sanitize-v850eq */
+  result = EXTEND16 (result);
+  GR[reg2] = result;
+  TRACE_LD (addr, result);
+/* start-sanitize-v850eq */
+    }
+/* end-sanitize-v850eq */
 }
 
 rrrrr,1010,dddddd,0:IV:::sld.w
 "sld.w <disp8>[ep], r<reg2>"
 {
-  COMPAT_1 (OP_500 ());
+  unsigned32 addr = EP + disp8;
+  unsigned32 result = load_mem (addr, 4);
+  GR[reg2] = result;
+  TRACE_LD (addr, result);
 }
 
 // start-sanitize-v850e
 rrrrr!0,0000110,dddd:IV:::sld.bu
+*v850e
+// start-sanitize-v850eq
+*v850eq
+"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
+// end-sanitize-v850eq
 "sld.bu <disp4>[ep], r<reg2>"
 {
-  unsigned long result;
-      
-  SAVE_1;
-  result = load_mem (State.regs[30] + disp4, 1);
-      
+  unsigned32 addr = EP + disp4;
+  unsigned32 result = load_mem (addr, 1);
   /* start-sanitize-v850eq */
-  if (PSW & PSW_US) {
-    trace_input ("sld.b", OP_LOAD16, 1);
-      
-    State.regs[ reg2 ] = EXTEND8 (result);
-  } else {
+  if (PSW & PSW_US)
+    {
+      result = EXTEND8 (result);
+      GR[reg2] = result;
+      TRACE_LD_NAME ("sld.b", addr, result);
+    }
+  else
+    {
   /* end-sanitize-v850eq */
-  trace_input ("sld.bu", OP_LOAD16, 1);
-  State.regs[ reg2 ] = result;
+  GR[reg2] = result;
+  TRACE_LD (addr, result);
   /* start-sanitize-v850eq */
-  }
+    }
   /* end-sanitize-v850eq */
-  trace_output (OP_LOAD16);
 }
 
 // end-sanitize-v850e
 // start-sanitize-v850e
 rrrrr!0,0000111,dddd:IV:::sld.hu
+*v850e
+// start-sanitize-v850eq
+*v850eq
+"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
+// end-sanitize-v850eq
 "sld.hu <disp5>[ep], r<reg2>"
 {
-  COMPAT_1 (OP_70 ());
+  unsigned32 addr = EP + disp5;
+  unsigned32 result = load_mem (addr, 2);
+  /* start-sanitize-v850eq */
+  if (PSW & PSW_US)
+    {
+      result = EXTEND16 (result);
+      GR[reg2] = result;
+      TRACE_LD_NAME ("sld.h", addr, result);
+    }
+  else
+    {
+/* end-sanitize-v850eq */
+  GR[reg2] = result;
+  TRACE_LD (addr, result);
+/* start-sanitize-v850eq */
+    }
+/* end-sanitize-v850eq */
 }
 
 // end-sanitize-v850e