* interp.c (hash): Update to be more accurate.

        (lookup_hash): Call hash rather than computing the hash
        code here.
        (do_format_1_2): Handle format 1 and format 2 instructions.
        Get operands correctly and call the target function.
        (do_format_6): Get operands correctly and call the target
        function.
        (do_formats_9_10): Rough cut so shift ops will work.
        (sim_resume): Tweak to deal with format 1 and format 2
        handling in a single funtion.  Don't update the PC
        for format 3 insns.  Fix typos.
        * simops.c: Slightly reorganize.  Add condition code handling
        to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
        and "not" instructions.
        * v850_sim.h (reg_t): Registers are 32bits.
        (_state): The V850 has 32 general registers.  Add a 32bit
        psw and pc register too.  Add accessor macros
Fixing lots of stuff.  Starting to add condition code support.  Basically
check pointing the work to date.

1 files changed, 35 insertions, 35 deletions

diff --git a/sim/v850/v850_sim.h b/sim/v850/v850_sim.h
index a840da1..b7402ae 100644
--- a/sim/v850/v850_sim.h
+++ b/sim/v850/v850_sim.h
@@ -13,7 +13,7 @@ typedef signed int int32;
 typedef signed long long int64;
 
 /* FIXME: V850 defines */
-typedef uint16 reg_t;
+typedef uint32 reg_t;
 
 struct simops 
 {
@@ -26,21 +26,9 @@ struct simops
 
 struct _state
 {
-  reg_t regs[16];		/* general-purpose registers */
-  reg_t cregs[16];	/* control registers */
-  int64 a[2];	/* accumulators */
-  uint8 SM;
-  uint8 EA;
-  uint8 DB;
-  uint8 IE;
-  uint8 RP;
-  uint8 MD;
-  uint8 FX;
-  uint8 ST;
-  uint8 F0;
-  uint8 F1;
-  uint8 C;
-  uint8 exe;
+  reg_t regs[32];		/* general-purpose registers */
+  reg_t pc;
+  reg_t psw;
   uint8 *imem;
   uint8 *dmem;
   int   exception;
@@ -49,16 +37,17 @@ struct _state
 extern uint16 OP[4];
 extern struct simops Simops[];
 
-#define PC	(State.cregs[2])
-#define PSW	(State.cregs[0])
-#define BPSW	(State.cregs[1])
-#define BPC	(State.cregs[3])
-#define RPT_C	(State.cregs[7])
-#define RPT_S	(State.cregs[8])
-#define RPT_E	(State.cregs[9])
-#define MOD_S	(State.cregs[10])
-#define MOD_E	(State.cregs[11])
-#define IBA	(State.cregs[14])
+#define PC	(State.pc)
+#define PSW	(State.psw)
+
+#define PSW_NP 0x80
+#define PSW_EP 0x40
+#define PSW_ID 0x20
+#define PSW_SAT 0x10
+#define PSW_CY 0x8
+#define PSW_OV 0x4
+#define PSW_S 0x2
+#define PSW_Z 0x1
 
 #define SEXT3(x)	((((x)&0x7)^(~3))+4)	
 
@@ -95,17 +84,28 @@ extern struct simops Simops[];
 
 #ifdef WORDS_BIGENDIAN
 
-#define RW(x)	(*((uint16 *)((x)+State.imem)))
-#define RLW(x)	(*((uint32 *)((x)+State.imem)))
-#define SW(addr,data)	RW(addr)=data
+#define RW(x)			(*((uint16 *)((x)+State.imem)))
+#define RLW(x)			(*((uint32 *)((x)+State.imem)))
+#define SW(addr,data)		RW(addr)=data
+#define READ_16(x)		(*((int16 *)(x)))
+#define WRITE_16(addr,data)	(*(int16 *)(addr)=data)	
+#define READ_64(x)		(*((int64 *)(x)))
+#define WRITE_64(addr,data)	(*(int64 *)(addr)=data)	
 
 #else
 
-uint32 get_longword_swap PARAMS ((uint16 x));
-uint16 get_word_swap PARAMS ((uint16 x));
-void write_word_swap PARAMS ((uint16 addr, uint16 data));
-#define SW(addr,data)	write_word_swap(addr,data)
-#define RW(x)	get_word_swap(x)
-#define RLW(x)	get_longword_swap(x)
+uint32 get_longword PARAMS ((uint8 *));
+uint16 get_word PARAMS ((uint8 *));
+int64 get_longlong PARAMS ((uint8 *));
+void write_word PARAMS ((uint8 *addr, uint16 data));
+void write_longlong PARAMS ((uint8 *addr, int64 data));
+
+#define SW(addr,data)		write_word((long)(addr)+State.imem,data)
+#define RW(x)			get_word((long)(x)+State.imem)
+#define RLW(x)			get_longword((long)(x)+State.imem)
+#define READ_16(x)		get_word(x)
+#define WRITE_16(addr,data)	write_word(addr,data)
+#define READ_64(x)		get_longlong(x)
+#define WRITE_64(addr,data)	write_longlong(addr,data)
 
 #endif /* not WORDS_BIGENDIAN */