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| author | DJ Delorie <dj@redhat.com> | 2008-02-06 00:40:05 +0000 |
|---|---|---|
| committer | DJ Delorie <dj@redhat.com> | 2008-02-06 00:40:05 +0000 |
| commit | c5fbc25baf8de20a337383d4785dd4e15da428b0 (patch) | |
| tree | 949d697d1bf9d65ba3a3bbabde25ec43fe9c9c49 /sim/v850/v850.igen | |
| parent | e5c4eb7a6c1d03decdb318b5a9e43719f207f460 (diff) | |
| download | gdb-c5fbc25baf8de20a337383d4785dd4e15da428b0.zip gdb-c5fbc25baf8de20a337383d4785dd4e15da428b0.tar.gz gdb-c5fbc25baf8de20a337383d4785dd4e15da428b0.tar.bz2 | |
Index: ChangeLog
* configure.ac (v850): V850 now has a testsuite.
* configure (v850): Likewise.
Index: testsuite/ChangeLog
* sim/v850/: New directory.
* sim/v850/allinsns.exp: New.
* sim/v850/bsh.cgs: New.
* sim/v850/div.cgs: New.
* sim/v850/divh.cgs: New.
* sim/v850/divh_3.cgs: New.
* sim/v850/divhu.cgs: New.
* sim/v850/divu.cgs: New.
* sim/v850/sar.cgs: New.
* sim/v850/satadd.cgs: New.
* sim/v850/satsub.cgs: New.
* sim/v850/satsubi.cgs: New.
* sim/v850/satsubr.cgs: New.
* sim/v850/shl.cgs: New.
* sim/v850/shr.cgs: New.
* sim/v850/testutils.cgs: New.
* sim/v850/testutils.inc: New.
Index: v850/ChangeLog
* simops.c (OP_C0): Correct saturation logic.
(OP_220): Likewise.
(OP_A0): Likewise.
(OP_660): Likewise.
(OP_80): Likewise.
* simops.c (OP_2A0): If the shift count is zero, clear the
carry.
(OP_A007E0): Likewise.
(OP_2C0): Likewise.
(OP_C007E0): Likewise.
(OP_280): Likewise.
(OP_8007E0): Likewise.
* simops.c (OP_2C207E0): Correct PSW flags for special divu
conditions.
(OP_2C007E0): Likewise, for div.
(OP_28207E0): Likewise, for divhu.
(OP_28007E0): Likewise, for divh. Also, sign-extend the correct
operand.
* v850.igen (divh): Likewise, for 2-op divh.
* v850.igen (bsh): Fix carry logic.
Diffstat (limited to 'sim/v850/v850.igen')
| -rw-r--r-- | sim/v850/v850.igen | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index 4796ea5..6617bd8 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -171,9 +171,9 @@ rrrrr,11111100000 + wwwww,01101000010:XII:::bsh GR[reg3] = value; PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); - if (value == 0) PSW |= PSW_Z; + if ((value & 0xffff) == 0) PSW |= PSW_Z; if (value & 0x80000000) PSW |= PSW_S; - if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY; + if (((value & 0xff) == 0) || ((value & 0xff00) == 0)) PSW |= PSW_CY; TRACE_ALU_RESULT (GR[reg3]); } @@ -358,28 +358,28 @@ rrrrr!0,000010,RRRRR!0:I:::divh if (op0 == 0xffffffff && op1 == 0x80000000) { - result = 0x80000000; - ov = 1; + PSW &= ~PSW_Z; + PSW |= PSW_OV | PSW_S; + State.regs[OP[1]] = 0x80000000; } - else if (op0 != 0) + else if (op0 == 0) { - result = op1 / op0; - ov = 0; + PSW |= PSW_OV; } else { - result = 0x0; - ov = 1; - } - - /* Compute the condition codes. */ - z = (result == 0); - s = (result & 0x80000000); + result = op1 / op0; + ov = 0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); - /* Store the result and condition codes. */ - State.regs[OP[1]] = result; - PSW &= ~(PSW_Z | PSW_S | PSW_OV); - PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0)); + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0)); + } trace_output (OP_REG_REG); |