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| author | Nick Clifton <nickc@redhat.com> | 2015-02-27 09:49:20 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2015-02-27 09:53:03 +0000 |
| commit | a3976a7c56ec803f6ba141576cc56afe02663a8a (patch) | |
| tree | ed44b1849b8358a65b98795721a8105f21e1f526 /sim/v850/v850.igen | |
| parent | 60abeae4f219a7a445d11ebaf72d2939413ffe80 (diff) | |
| download | gdb-a3976a7c56ec803f6ba141576cc56afe02663a8a.zip gdb-a3976a7c56ec803f6ba141576cc56afe02663a8a.tar.gz gdb-a3976a7c56ec803f6ba141576cc56afe02663a8a.tar.bz2 | |
Fixes problems building the V850 simulator introduced with the previous delta.
* sim-main.h (reg64_t): New type.
(v850_regs): Add selID_sregs field.
(VR, SAT16, SAT32, ABS16, ABS32 ): New macros.
* v850-dc: Add fields for v850e3v5 instructions.
* v850.igen (cvtf.dl): Use correctly signed local value.
(cvtf.dw, cvtf.sw, trncf.dul, trncf.dl, trncf.sul, trncf.sw):
Likewise.
* interp.c: Fix old style function declarations.
* simops.c: Likewise.
Diffstat (limited to 'sim/v850/v850.igen')
| -rw-r--r-- | sim/v850/v850.igen | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index 0270963..41a9075 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -2561,7 +2561,7 @@ rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl *v850e3v5 "cvtf.dl r<reg2e>, r<reg3e>" { - unsigned64 ans; + signed64 ans; sim_fpu wop; sim_fpu_status status; @@ -2604,7 +2604,7 @@ rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw *v850e3v5 "cvtf.dw r<reg2e>, r<reg3>" { - uint32 ans; + int32 ans; sim_fpu wop; sim_fpu_status status; @@ -2712,7 +2712,7 @@ rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw *v850e3v5 "cvtf.sw r<reg2>, r<reg3>" { - uint32 ans; + int32 ans; sim_fpu wop; sim_fpu_status status; @@ -3471,7 +3471,7 @@ rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul *v850e3v5 "trncf.dul r<reg2e>, r<reg3e>" { - signed64 ans; + unsigned64 ans; sim_fpu wop; sim_fpu_status status; @@ -3493,7 +3493,7 @@ rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw *v850e3v5 "trncf.dw r<reg2e>, r<reg3>" { - uint32 ans; + int32 ans; sim_fpu wop; sim_fpu_status status; @@ -3555,7 +3555,7 @@ rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul *v850e3v5 "trncf.sul r<reg2>, r<reg3e>" { - signed64 ans; + unsigned64 ans; sim_fpu wop; sim_fpu_status status; @@ -3575,7 +3575,7 @@ rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw *v850e3v5 "trncf.sw r<reg2>, r<reg3>" { - uint32 ans; + int32 ans; sim_fpu wop; sim_fpu_status status; |