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author | Jeff Law <law@redhat.com> | 1996-08-30 16:35:10 +0000 |
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committer | Jeff Law <law@redhat.com> | 1996-08-30 16:35:10 +0000 |
commit | 83fc3bac9fd75bd785cf0016ca429b301c30fabd (patch) | |
tree | f91c87d77641e63480d36b44dd479dc30282a995 /sim/v850/simops.c | |
parent | 76a61985c130464e743adb6369ccfb1753c090a4 (diff) | |
download | gdb-83fc3bac9fd75bd785cf0016ca429b301c30fabd.zip gdb-83fc3bac9fd75bd785cf0016ca429b301c30fabd.tar.gz gdb-83fc3bac9fd75bd785cf0016ca429b301c30fabd.tar.bz2 |
* interp.c (hash): Fix.
* interp.c (do_format_8): Get operands correctly and
call the target function.
* simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
Diffstat (limited to 'sim/v850/simops.c')
-rw-r--r-- | sim/v850/simops.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/sim/v850/simops.c b/sim/v850/simops.c index f763d02..1586b11 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -1306,24 +1306,78 @@ OP_20 () void OP_7C0 () { + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + op1 = OP[1] & 0x7; + temp = OP[2]; + temp = (temp << 16) >> 16; + op2 = temp; + temp = get_byte (State.mem + op0 + op2); + State.sregs[5] &= ~PSW_Z; + if ((temp & (1 << op1)) == 0) + State.sregs[5] |= PSW_Z; + temp |= ~(1 << op1); + put_byte (State.mem + op0 + op2, temp); } /* not1 */ void OP_47C0 () { + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + op1 = OP[1] & 0x7; + temp = OP[2]; + temp = (temp << 16) >> 16; + op2 = temp; + temp = get_byte (State.mem + op0 + op2); + State.sregs[5] &= ~PSW_Z; + if ((temp & (1 << op1)) == 0) + State.sregs[5] |= PSW_Z; + temp ^= ~(1 << op1); + put_byte (State.mem + op0 + op2, temp); } /* clr1 */ void OP_87C0 () { + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + op1 = OP[1] & 0x7; + temp = OP[2]; + temp = (temp << 16) >> 16; + op2 = temp; + temp = get_byte (State.mem + op0 + op2); + State.sregs[5] &= ~PSW_Z; + if ((temp & (1 << op1)) == 0) + State.sregs[5] |= PSW_Z; + temp &= ~(1 << op1); + put_byte (State.mem + op0 + op2, temp); } /* tst1 */ void OP_C7C0 () { + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + op1 = OP[1] & 0x7; + temp = OP[2]; + temp = (temp << 16) >> 16; + op2 = temp; + temp = get_byte (State.mem + op0 + op2); + State.sregs[5] &= ~PSW_Z; + if ((temp & (1 << op1)) == 0) + State.sregs[5] |= PSW_Z; } /* di */ |