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| author | Jim Wilson <wilson@tuliptree.org> | 2002-09-30 20:11:08 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@tuliptree.org> | 2002-09-30 20:11:08 +0000 |
| commit | 30458d39d6f791293f844ab9f75c4f465d52e74c (patch) | |
| tree | 8a55b9eea403c0a40d598cffec3c9f4d8bbff7bf /sim/v850/simops.c | |
| parent | 28ee05e92474f1a72e289ff06050351938b8f807 (diff) | |
| download | gdb-30458d39d6f791293f844ab9f75c4f465d52e74c.zip gdb-30458d39d6f791293f844ab9f75c4f465d52e74c.tar.gz gdb-30458d39d6f791293f844ab9f75c4f465d52e74c.tar.bz2 | |
Fix handling of v850e bit-twiddle instructions.
* simops.c (OP_E6077E0): And op1 with 7 after reading register, not
before.
(BIT_CHANGE_OP): Likewise.
Diffstat (limited to 'sim/v850/simops.c')
| -rw-r--r-- | sim/v850/simops.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/v850/simops.c b/sim/v850/simops.c index eba728f..0404523 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -1897,7 +1897,7 @@ OP_E607E0 (void) temp = load_mem (State.regs[ OP[0] ], 1); PSW &= ~PSW_Z; - if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0) + if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0) PSW |= PSW_Z; trace_output (OP_BIT); @@ -1924,7 +1924,7 @@ OP_22207E0 (void) \ trace_input (name, OP_BIT_CHANGE, 0); \ \ - bit = 1 << State.regs[ OP[1] & 0x7 ]; \ + bit = 1 << (State.regs[ OP[1] ] & 0x7); \ temp = load_mem (State.regs[ OP[0] ], 1); \ \ PSW &= ~PSW_Z; \ |