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| author | Andrew Cagney <cagney@redhat.com> | 1997-09-19 00:50:19 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-09-19 00:50:19 +0000 |
| commit | 60fe0e06a825b1e36c35534d53d2196f01a3d74d (patch) | |
| tree | 6e66e7128e00cc54326612eef74cbd8d40e582db /sim/v850/sim-main.h | |
| parent | 46ad7d6ccb1590b1a2fee9c1ab06a5e3f2622921 (diff) | |
| download | gdb-60fe0e06a825b1e36c35534d53d2196f01a3d74d.zip gdb-60fe0e06a825b1e36c35534d53d2196f01a3d74d.tar.gz gdb-60fe0e06a825b1e36c35534d53d2196f01a3d74d.tar.bz2 | |
Fix cmov insn.
Diffstat (limited to 'sim/v850/sim-main.h')
| -rw-r--r-- | sim/v850/sim-main.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h index a4c57af..2d1bf6a 100644 --- a/sim/v850/sim-main.h +++ b/sim/v850/sim-main.h @@ -224,6 +224,10 @@ sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \ PC, sim_core_write_map, (ADDR), (DATA)) +/* compare cccc field against PSW */ +unsigned int condition_met (unsigned code); + + /* Debug/tracing calls */ enum op_types @@ -310,6 +314,19 @@ do { \ } \ } while (0) +#define TRACE_ALU_INPUT3(IN0, IN1, IN2) \ +do { \ + if (TRACE_ALU_P (CPU)) { \ + trace_module = "alu"; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_values[0] = (IN0); \ + trace_values[1] = (IN1); \ + trace_values[2] = (IN2); \ + trace_num_values = 3; \ + } \ +} while (0) + #define TRACE_ALU_RESULT(RESULT) \ do { \ if (TRACE_ALU_P (CPU)) { \ |