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| author | Andrew Cagney <cagney@redhat.com> | 1997-09-19 02:20:02 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-09-19 02:20:02 +0000 |
| commit | bd4c35cc6dc11b11321550b8d4d873571cb0b92c (patch) | |
| tree | da146d3fed4c5591a19212440d9afd8bf787244c /sim/v850/sim-main.h | |
| parent | 1379884be1c0d2a8083228a0bedeaf45a4b8874d (diff) | |
| download | gdb-bd4c35cc6dc11b11321550b8d4d873571cb0b92c.zip gdb-bd4c35cc6dc11b11321550b8d4d873571cb0b92c.tar.gz gdb-bd4c35cc6dc11b11321550b8d4d873571cb0b92c.tar.bz2 | |
Fix cmov immed.
Diffstat (limited to 'sim/v850/sim-main.h')
| -rw-r--r-- | sim/v850/sim-main.h | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h index 2d1bf6a..99b508c 100644 --- a/sim/v850/sim-main.h +++ b/sim/v850/sim-main.h @@ -225,7 +225,7 @@ sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \ /* compare cccc field against PSW */ -unsigned int condition_met (unsigned code); +int condition_met (unsigned code); /* Debug/tracing calls */ @@ -334,6 +334,17 @@ do { \ } \ } while (0) +#define TRACE_BRANCH0() \ +do { \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = "branch"; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_num_values = 0; \ + trace_result (1, (nia)); \ + } \ +} while (0) + #define TRACE_BRANCH1(IN1) \ do { \ if (TRACE_BRANCH_P (CPU)) { \ @@ -380,10 +391,13 @@ do { \ #define trace_result(HAS_RESULT, RESULT) #define TRACE_ALU_INPUT0() -#define TRACE_ALU_INPUT1(IN1) -#define TRACE_ALU_INPUT2(IN1, IN2) +#define TRACE_ALU_INPUT1(IN0) +#define TRACE_ALU_INPUT2(IN0, IN1) +#define TRACE_ALU_INPUT2(IN0, IN1) +#define TRACE_ALU_INPUT2(IN0, IN1 INS2) #define TRACE_ALU_RESULT(RESULT) +#define TRACE_BRANCH0() #define TRACE_BRANCH1(IN1) #define TRACE_BRANCH2(IN1, IN2) #define TRACE_BRANCH2(IN1, IN2, IN3) |