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authorStu Grossman <grossman@cygnus>1996-09-28 01:38:45 +0000
committerStu Grossman <grossman@cygnus>1996-09-28 01:38:45 +0000
commit88777ce2a6681104eed8c7a15df49acf03935134 (patch)
tree09c0aa03669c7dd8b87bf117e7f84ed5f7b92131 /sim/v850/interp.c
parent8d622d4c7c24d005fa3b0affd6d8386171769e9e (diff)
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* gencode.c (write_opcodes): Output hex values for opcode mask
and patterns. * interp.c (sim_resume): Save and restore PC from the appropriate register. * (sim_fetch_register sim_store_register): Fix byte-order problem with reading and writing registers. * simops.c (OP_FFFF): Implement pseudo-breakpoint insn.
Diffstat (limited to 'sim/v850/interp.c')
-rw-r--r--sim/v850/interp.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index ce70743..77b7c66 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -287,10 +287,10 @@ sim_open (args)
{
#ifdef DEBUG
if (strcmp (args, "-t") == 0)
- d10v_debug = DEBUG;
+ v850_debug = DEBUG;
else
#endif
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",args);
+ (*v850_callback->printf_filtered) (v850_callback, "ERROR: unsupported option(s): %s\n",args);
}
/* put all the opcodes in the hash table */
@@ -342,6 +342,8 @@ sim_resume (step, siggnal)
uint32 inst, opcode;
reg_t oldpc;
+ PC = State.sregs[0];
+
if (step)
State.exception = SIGTRAP;
else
@@ -399,6 +401,8 @@ sim_resume (step, siggnal)
}
}
while (!State.exception);
+
+ State.sregs[0] = PC;
}
int
@@ -462,7 +466,7 @@ sim_fetch_register (rn, memory)
int rn;
unsigned char *memory;
{
- *(uint32 *)memory = State.regs[rn];
+ put_word (memory, State.regs[rn]);
}
void
@@ -470,7 +474,7 @@ sim_store_register (rn, memory)
int rn;
unsigned char *memory;
{
- State.regs[rn]= *(uint32 *)memory;
+ State.regs[rn] = get_word (memory);
}
int