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author | Andrew Cagney <cagney@redhat.com> | 1997-09-04 10:10:02 +0000 |
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committer | Andrew Cagney <cagney@redhat.com> | 1997-09-04 10:10:02 +0000 |
commit | da3a66e5ca77e7c0c33957631800f237f05bafcb (patch) | |
tree | 1cad33dfadc789f011cb161b802f1707f186c43a /sim/v850/Makefile.in | |
parent | 6dbaff8f6067e91995adc90e5c8939de41c56e9a (diff) | |
download | gdb-da3a66e5ca77e7c0c33957631800f237f05bafcb.zip gdb-da3a66e5ca77e7c0c33957631800f237f05bafcb.tar.gz gdb-da3a66e5ca77e7c0c33957631800f237f05bafcb.tar.bz2 |
Replace memory model with one from sim/common directory.
Diffstat (limited to 'sim/v850/Makefile.in')
-rw-r--r-- | sim/v850/Makefile.in | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sim/v850/Makefile.in b/sim/v850/Makefile.in index 7f5f222..f067eb6 100644 --- a/sim/v850/Makefile.in +++ b/sim/v850/Makefile.in @@ -25,8 +25,10 @@ SIM_OBJS = interp.o table.o simops.o \ sim-endian.o \ sim-events.o \ sim-hload.o \ + sim-hrw.o \ sim-io.o \ sim-load.o \ + sim-memopt.o \ sim-module.o \ sim-options.o \ sim-profile.o \ |