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| author | Andrew Cagney <cagney@redhat.com> | 1997-09-12 05:56:38 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-09-12 05:56:38 +0000 |
| commit | 410230cf6d65003b0595a7ef712b671d1bb77b0d (patch) | |
| tree | c6ba4f2a0edfd794857fce8061b26e448ef8a182 /sim/v850/ChangeLog | |
| parent | 944deab68edff4993da304bc2ed56827310b11ca (diff) | |
| download | gdb-410230cf6d65003b0595a7ef712b671d1bb77b0d.zip gdb-410230cf6d65003b0595a7ef712b671d1bb77b0d.tar.gz gdb-410230cf6d65003b0595a7ef712b671d1bb77b0d.tar.bz2 | |
Check reserved bits before executing instructions.
Make v850[eq] the the default simulator.
Report illegal instructions.
Include v850e instructions in v850eq.
Diffstat (limited to 'sim/v850/ChangeLog')
| -rw-r--r-- | sim/v850/ChangeLog | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog index feab6ef..6ac5cb4 100644 --- a/sim/v850/ChangeLog +++ b/sim/v850/ChangeLog @@ -1,3 +1,26 @@ +Fri Sep 12 15:11:03 1997 Andrew Cagney <cagney@b1.cygnus.com> + +start-sanitize-v850eq + * v850.igen (prepare, ...): Add to v850eq architecture. + +end-sanitize-v850eq +start-sanitize-v850e + * interp.c (sim_open): Default to v850eq. + +end-sanitize-v850e +start-sanitize-v850eq + + * interp.c (sim_open): Default to v850e. +end-sanitize-v850eq + * sim-main.h (signal.h): Include. + + * v850.igen (illegal): Report/halt illegal instructions. + + * Makefile.in (SIM_EXTRA_CFLAGS): Add SIM_RESERVED_BITS. + + * configure.in: Add reserved bits option. + * configure: Regenerate. + Thu Sep 11 08:40:03 1997 Andrew Cagney <cagney@b1.cygnus.com> * interp.c (sim_open): Use sim_do_commandf instead of asprintf. |