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| author | Ian Carmichael <iancarm@cygnus> | 1998-01-16 19:27:02 +0000 |
|---|---|---|
| committer | Ian Carmichael <iancarm@cygnus> | 1998-01-16 19:27:02 +0000 |
| commit | 1e1e3b618f80c51d59a6ebeefe282bb920d4a0e8 (patch) | |
| tree | 5a6580db4e0a13dbaf7917655c3e1734690f3c9c /sim/txvu/dma.h | |
| parent | 8e12359329fd48edc455afa2f80922eca7b79a7d (diff) | |
| download | gdb-1e1e3b618f80c51d59a6ebeefe282bb920d4a0e8.zip gdb-1e1e3b618f80c51d59a6ebeefe282bb920d4a0e8.tar.gz gdb-1e1e3b618f80c51d59a6ebeefe282bb920d4a0e8.tar.bz2 | |
* Initial Device Support
*
*Modified Files:
* .Sanitize ChangeLog
*Added Files:
* Makefile.in README.Cygnus config.in configure configure.in
* device.c device.h dma.c dma.h engine-sky.c gencode.c gpuif.c
* gpuif.h hardware.c hardware.h interp.c m16.igen mdmx.igen
* mips.dc mips.igen pke0.c pke0.h pke1.c pke1.h r5900.igen
* sim-main.h tconfig.in vr5400.igen vu0.c vu0.h vu1.c vu1.h
Diffstat (limited to 'sim/txvu/dma.h')
| -rw-r--r-- | sim/txvu/dma.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/sim/txvu/dma.h b/sim/txvu/dma.h new file mode 100644 index 0000000..dc2fcb7 --- /dev/null +++ b/sim/txvu/dma.h @@ -0,0 +1,46 @@ +/* Copyright (C) 1998, Cygnus Solutions + + */ + +#ifndef DMA_H_ +#define DMA_H_ + +#include "sim-main.h" + +void dma_attach(SIM_DESC sd); + +#define DMA_REGISTER_WINDOW_START 0x10001000 + +#define DMA_D0_CHCR_ADDR 0x10001000 +#define DMA_D0_MADR_ADDR 0x10001010 +#define DMA_D0_QWC_ADDR 0x10001020 +#define DMA_D0_TADR_ADDR 0x10001030 +#define DMA_D0_ASR0_ADDR 0x10001040 +#define DMA_D0_ASR1_ADDR 0x10001050 + +#define DMA_D1_CHCR_ADDR 0x10001100 +#define DMA_D1_MADR_ADDR 0x10001110 +#define DMA_D1_QWC_ADDR 0x10001120 +#define DMA_D1_TADR_ADDR 0x10001130 +#define DMA_D1_ASR0_ADDR 0x10001140 +#define DMA_D1_ASR1_ADDR 0x10001150 + +#define DMA_D2_CHCR_ADDR 0x10001200 +#define DMA_D2_MADR_ADDR 0x10001210 +#define DMA_D2_QWC_ADDR 0x10001220 +#define DMA_D2_TADR_ADDR 0x10001230 +#define DMA_D2_ASR0_ADDR 0x10001240 +#define DMA_D2_ASR1_ADDR 0x10001250 + +#define DMA_D_CTRL 0x10001c00 +#define DMA_D_STAT 0x10001c10 +#define DMA_D_PCR 0x10001c20 +#define DMA_D_SQWC 0x10001c30 +#define DMA_D_RBSR 0x10001c40 +#define DMA_D_RBOR 0x10001c50 +#define DMA_D_STADR 0x10001c60 + +#define DMA_REGISTER_WINDOW_END 0x10001c70 +#define DMA_REGISTER_WINDOW_SIZE (DMA_REGISTER_WINDOW_END - DMA_REGISTER_WINDOW_START) + +#endif |