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| author | Andrew Cagney <cagney@redhat.com> | 2000-07-04 05:00:54 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2000-07-04 05:00:54 +0000 |
| commit | 6c29acca43b2c78b7668b5c8c6676181303b9cfd (patch) | |
| tree | ccea8802dbc4a003671fc4627f73ffa0f77d5cdc /sim/tic80/tic80.ic | |
| parent | 78492fde3d8e2784f72284ad97fc1fcd7544a860 (diff) | |
| download | gdb-6c29acca43b2c78b7668b5c8c6676181303b9cfd.zip gdb-6c29acca43b2c78b7668b5c8c6676181303b9cfd.tar.gz gdb-6c29acca43b2c78b7668b5c8c6676181303b9cfd.tar.bz2 | |
TIc80 simulator.
Diffstat (limited to 'sim/tic80/tic80.ic')
| -rw-r--r-- | sim/tic80/tic80.ic | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/sim/tic80/tic80.ic b/sim/tic80/tic80.ic new file mode 100644 index 0000000..de81d14 --- /dev/null +++ b/sim/tic80/tic80.ic @@ -0,0 +1,52 @@ +cache:Dest:Dest: +cache:Dest:rDest:signed_word *:(&(CPU)->reg[Dest]) +# +cache:Source1:Source1: +cache:Source1:vSource1:signed_word:(GPR (Source1) + 0) +#cache:Source1:vSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1]) +# +cache:Source2:Source2: +cache:Source2:vSource2:signed_word:(GPR (Source2) + 0) +#cache:Source2:vSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2]) +# +cache:Source:Source: +cache:Source:vSource:signed_word:(GPR (Source) + 0) +#cache:Source:vSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source]) +# +cache:IndOff:IndOff: +cache:IndOff:rIndOff:signed_word:(GPR (IndOff) + 0) +#cache:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff]) +# +cache:Base:Base: +cache:Base:vBase:signed_word:(GPR (Base) + 0) +cache:Base:rBase:signed_word*:(&GPR (Base)) +#cache:Base:vBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base]) +# +cache:Link:Link: +cache:Link:rLink:signed_word*:(&(CPU)->reg[Link]) +# +# Trap Number +cache:UTN:UTN: +cache:INDTR:INDTR: +cache:INDTR:UTN:unsigned_word:(INDTR == 0 ? 0 : (CPU)->reg[INDTR]) +# +cache:A:A: +# +cache:SignedImmediate:SignedImmediate: +cache:SignedImmediate:vSource1:signed_word:SEXT (SignedImmediate, 14) +# +cache:UnsignedImmediate:UnsignedImmediate: +cache:UnsignedImmediate:vSource1:signed_word:UnsignedImmediate +# +cache:BITNUM:BITNUM: +cache:Code:Code: +cache:BITNUM:bitnum:int:(~BITNUM) & 0x1f + +# +cache:SignedOffset:SignedOffset: +cache:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14) +# +cache:UCRN:UCRN: +cache:INDCR:INDCR: +cache:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0) +#cache:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR]) |