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| author | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
| commit | 37a684b84d5c722848ebdc7203052d65c6b35e30 (patch) | |
| tree | 3d7fa5b15efab746e9b8cc87449fa8664b6ed359 /sim/tic80/sim-calls.c | |
| parent | 77bd8dfa1f3678ea3c3d05f40de29a36802d21f5 (diff) | |
| download | gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.zip gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.gz gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.bz2 | |
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
Diffstat (limited to 'sim/tic80/sim-calls.c')
| -rw-r--r-- | sim/tic80/sim-calls.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/sim/tic80/sim-calls.c b/sim/tic80/sim-calls.c index 3677d8c..dd54184 100644 --- a/sim/tic80/sim-calls.c +++ b/sim/tic80/sim-calls.c @@ -177,7 +177,9 @@ sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length) void sim_fetch_register (SIM_DESC sd, int regnr, unsigned char *buf) { - if (regnr >= R0_REGNUM && regnr <= Rn_REGNUM) + if (regnr == R0_REGNUM) + memset (buf, 0, sizeof (unsigned32)); + else if (regnr > R0_REGNUM && regnr <= Rn_REGNUM) *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM]); else if (regnr == PC_REGNUM) *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->cia.ip); |