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| author | Andrew Cagney <cagney@redhat.com> | 1997-05-19 03:42:33 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-19 03:42:33 +0000 |
| commit | f03b093cd34bc352ad89334a43a34b00a5e5c60c (patch) | |
| tree | b9d428d2bdf6dd5f5f5a25a7df7580c3836af9e4 /sim/tic80/interp.c | |
| parent | 11ab132f168d3c24d4b4d743d86599973b17e3f2 (diff) | |
| download | gdb-f03b093cd34bc352ad89334a43a34b00a5e5c60c.zip gdb-f03b093cd34bc352ad89334a43a34b00a5e5c60c.tar.gz gdb-f03b093cd34bc352ad89334a43a34b00a5e5c60c.tar.bz2 | |
o Implement generic halt/restart/abort module.
Use in tic80 and d30v simulators.
o Add signal hook to sim-core module
Diffstat (limited to 'sim/tic80/interp.c')
| -rw-r--r-- | sim/tic80/interp.c | 21 |
1 files changed, 5 insertions, 16 deletions
diff --git a/sim/tic80/interp.c b/sim/tic80/interp.c index 24cfad1..24c86f6 100644 --- a/sim/tic80/interp.c +++ b/sim/tic80/interp.c @@ -36,16 +36,8 @@ #endif #endif -void -engine_init (SIM_DESC sd) -{ - memset (&STATE_CPU (sd, 0)->reg, 0, sizeof STATE_CPU (sd, 0)->reg); - memset (&STATE_CPU (sd, 0)->cia, 0, sizeof STATE_CPU (sd, 0)->cia); - CPU_STATE (STATE_CPU (sd, 0)) = sd; -} - -/* Mechanisms for stopping/restarting the simulation */ +#if 0 void engine_error (SIM_DESC sd, @@ -59,13 +51,7 @@ engine_error (SIM_DESC sd, sim_io_evprintf (sd, fmt, ap); va_end (ap); - if (sd->halt_ok) - { - sim_io_eprintf (sd, "\n"); - engine_halt (sd, cpu, cia, sim_stopped, SIGABRT); - } - else - sim_io_error (sd, " - aborting simulation"); + sim_halt (sd, cpu, NULL, cia, sim_stopped, SIGABRT); } void @@ -139,3 +125,6 @@ engine_step (SIM_DESC sd) engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP); } } + +#endif + |