c80 simulator fixes.

1 files changed, 22 insertions, 18 deletions

diff --git a/sim/tic80/insns b/sim/tic80/insns
index 5a4110b..d924005 100644
--- a/sim/tic80/insns
+++ b/sim/tic80/insns
@@ -633,7 +633,6 @@ instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink,
 // ld[{.b.h.d}]
 void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 	unsigned32 addr;
-	unsigned64 u64;
 	switch (sz)
 	  {
 	  case 0:
@@ -655,15 +654,18 @@ void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int
 	    GPR(Dest) = MEM (signed, addr, 4);
 	    break;
 	  case 3:
-	    if (Dest & 0x1)
-	      engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
-	                    cia.ip, Dest);
-	    addr = Base + (S ? (Offset << 3) : Offset);
-	    if (m)
-	      *rBase = addr;
-	    u64 = MEM (signed, addr, 8);
-	    GPR(Dest) = (unsigned32) u64;
-	    GPR(Dest+1) = (unsigned32) (u64 >> 32);
+	    {
+	      signed64 val;
+	      if (Dest & 0x1)
+	        engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
+	                      cia.ip, Dest);
+	      addr = Base + (S ? (Offset << 3) : Offset);
+	      if (m)
+	        *rBase = addr;
+	      val = MEM (signed, addr, 8);
+	      GPR(Dest + 1) = VH4_8 (val);
+	      GPR(Dest + 0) = VL4_8 (val);
+	    }
 	    break;
 	  default:
 	    addr = -1;
@@ -898,7 +900,6 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
 // st[{.b|.h|.d}]
 void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 	unsigned32 addr;
-	unsigned64 u64;
 	switch (sz)
 	  {
 	  case 0:
@@ -914,13 +915,16 @@ void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , in
 	    STORE (addr, 4, GPR(Source));
 	    break;
 	  case 3:
-	    if (Source & 0x1)
-	      engine_error (SD, CPU, cia, "0x%lx: st.d with odd source register %d",
-	                    cia.ip, Source);
-	    addr = Base + (S ? (Offset << 3) : Offset);
-	    u64 = GPR (Source);
-	    u64 |= (((unsigned64) GPR (Source+1)) << 32);
-	    STORE (addr, 8, u64);
+	    {
+	      signed64 val;
+	      if (Source & 0x1)
+	        engine_error (SD, CPU, cia,
+	                      "0x%lx: st.d with odd source register %d",
+	                      cia.ip, Source);
+	      addr = Base + (S ? (Offset << 3) : Offset);
+	      val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
+	      STORE (addr, 8, val);
+	    }
 	    break;
 	  default:
 	    addr = -1;