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| author | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
| commit | 37a684b84d5c722848ebdc7203052d65c6b35e30 (patch) | |
| tree | 3d7fa5b15efab746e9b8cc87449fa8664b6ed359 /sim/tic80/ic | |
| parent | 77bd8dfa1f3678ea3c3d05f40de29a36802d21f5 (diff) | |
| download | gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.zip gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.gz gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.bz2 | |
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
Diffstat (limited to 'sim/tic80/ic')
| -rw-r--r-- | sim/tic80/ic | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/sim/tic80/ic b/sim/tic80/ic index 0fbbb5e..54a2550 100644 --- a/sim/tic80/ic +++ b/sim/tic80/ic @@ -2,19 +2,25 @@ compute:Dest:Dest: compute:Dest:rDest:signed_word *:(&(CPU)->reg[Dest]) # compute:Source1:Source1: -compute:Source1:rSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1]) +compute:Source1:vSource1:signed_word:(GPR (Source1) + 0) +#compute:Source1:vSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1]) # compute:Source2:Source2: -compute:Source2:rSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2]) +compute:Source2:vSource2:signed_word:(GPR (Source2) + 0) +#compute:Source2:vSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2]) # compute:Source:Source: -compute:Source:rSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source]) +compute:Source:vSource:signed_word:(GPR (Source) + 0) +#compute:Source:vSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source]) # compute:IndOff:IndOff: -compute:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff]) +compute:IndOff:rIndOff:signed_word:(GPR (IndOff) + 0) +#compute:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff]) # compute:Base:Base: -compute:Base:rBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base]) +compute:Base:vBase:signed_word:(GPR (Base) + 0) +compute:Base:rBase:signed_word:(&GPR (Base)) +#compute:Base:vBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base]) # compute:Link:Link: compute:Link:rLink:signed_word:(&(CPU)->reg[Link]) @@ -40,4 +46,5 @@ compute:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14) # compute:UCRN:UCRN: compute:INDCR:INDCR: -compute:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR]) +compute:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0) +#compute:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR]) |