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author | Andrew Cagney <cagney@redhat.com> | 1998-01-31 06:23:41 +0000 |
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committer | Andrew Cagney <cagney@redhat.com> | 1998-01-31 06:23:41 +0000 |
commit | 9ec6741b177fbd4d872a13002d540b60b11e4b78 (patch) | |
tree | 882348d86144658f9148f517f17c39dabe54df1e /sim/tic80/cpu.h | |
parent | 5266a484f4aa49a9ea52adbca949f6224ec2fcee (diff) | |
download | gdb-9ec6741b177fbd4d872a13002d540b60b11e4b78.zip gdb-9ec6741b177fbd4d872a13002d540b60b11e4b78.tar.gz gdb-9ec6741b177fbd4d872a13002d540b60b11e4b78.tar.bz2 |
igen: Fix SMP simulator generator support.
Use the bfd-processor name in the sim-engine switch.
Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
Update
mips: Fill in bfd-processor field of model records so that
they match ../bfd/archures.
Diffstat (limited to 'sim/tic80/cpu.h')
-rw-r--r-- | sim/tic80/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/sim/tic80/cpu.h b/sim/tic80/cpu.h index 4124512..6801c04 100644 --- a/sim/tic80/cpu.h +++ b/sim/tic80/cpu.h @@ -151,7 +151,8 @@ struct _sim_cpu { sim_cpu_base base; }; -#define CPU_CIA(CPU) ((CPU)->cia) +#define CIA_GET(CPU) ((CPU)->cia) +#define CIA_SET(CPU,VAL) ((CPU)->cia = (VAL)) #define GPR(N) ((CPU)->reg[N]) #define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL)) |