diff options
| author | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
| commit | 37a684b84d5c722848ebdc7203052d65c6b35e30 (patch) | |
| tree | 3d7fa5b15efab746e9b8cc87449fa8664b6ed359 /sim/tic80/cpu.h | |
| parent | 77bd8dfa1f3678ea3c3d05f40de29a36802d21f5 (diff) | |
| download | gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.zip gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.gz gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.bz2 | |
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
Diffstat (limited to 'sim/tic80/cpu.h')
| -rw-r--r-- | sim/tic80/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/tic80/cpu.h b/sim/tic80/cpu.h index 0027af0..d3d14b6 100644 --- a/sim/tic80/cpu.h +++ b/sim/tic80/cpu.h @@ -152,6 +152,7 @@ struct _sim_cpu { }; #define GPR(N) ((CPU)->reg[N]) +#define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL)) #define ACC(N) ((CPU)->acc[N]) #define CR(N) ((CPU)->cr[tic80_index2cr ((N))]) |