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| author | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
| commit | 37a684b84d5c722848ebdc7203052d65c6b35e30 (patch) | |
| tree | 3d7fa5b15efab746e9b8cc87449fa8664b6ed359 /sim/tic80/Makefile.in | |
| parent | 77bd8dfa1f3678ea3c3d05f40de29a36802d21f5 (diff) | |
| download | gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.zip gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.gz gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.bz2 | |
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
Diffstat (limited to 'sim/tic80/Makefile.in')
| -rw-r--r-- | sim/tic80/Makefile.in | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/tic80/Makefile.in b/sim/tic80/Makefile.in index 0e9dc25..dbfb4b6 100644 --- a/sim/tic80/Makefile.in +++ b/sim/tic80/Makefile.in @@ -92,6 +92,7 @@ tmp-igen: $(srcdir)/dc $(srcdir)/insns $(srcdir)/ic ../igen/igen -F f \ -G direct-access \ -G delayed-branch \ + -G zero-r0 \ -F short,emul \ -B 32 -H 31 \ -o $(srcdir)/dc \ |