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author | Andrew Cagney <cagney@redhat.com> | 1997-04-22 17:46:07 +0000 |
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committer | Andrew Cagney <cagney@redhat.com> | 1997-04-22 17:46:07 +0000 |
commit | 15c1649391b66df7e721377daa248721ab3e58eb (patch) | |
tree | cbc9fca2a3287bf2882499101225fd5213f44ad4 /sim/tic80/Makefile.in | |
parent | 81f464815db9a9fc4209c7eb6eb7ea341b78b76e (diff) | |
download | gdb-15c1649391b66df7e721377daa248721ab3e58eb.zip gdb-15c1649391b66df7e721377daa248721ab3e58eb.tar.gz gdb-15c1649391b66df7e721377daa248721ab3e58eb.tar.bz2 |
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a.
Diffstat (limited to 'sim/tic80/Makefile.in')
-rw-r--r-- | sim/tic80/Makefile.in | 141 |
1 files changed, 141 insertions, 0 deletions
diff --git a/sim/tic80/Makefile.in b/sim/tic80/Makefile.in new file mode 100644 index 0000000..2d0c8d1 --- /dev/null +++ b/sim/tic80/Makefile.in @@ -0,0 +1,141 @@ +# Makefile for blah ... +# Copyright blah ... + + + +## COMMON_PRE_CONFIG_FRAG + +# These variables are given default values in COMMON_PRE_CONFIG_FRAG. +# We override the ones we need to here. +# Not all of these need to be mentioned, only the necessary ones. + +# List of object files, less common parts. +SIM_OBJS = sim-endian.o sim-bits.o sim-config.o interp.o \ + support.o idecode.o semantics.o itable.o \ + sim-calls.o \ + sim-events.o \ + sim-core.o \ + sim-io.o \ + sim-utils.o \ + sim-load.o \ + sim-options.o \ + sim-trace.o + +# List of extra dependencies. +# Generally this consists of simulator specific files included by sim-main.h. +SIM_EXTRA_DEPS = itable.h idecode.h cpu.h alu.h + +# List of generators +SIM_GEN=tmp-igen + +# List of flags to always pass to $(CC). +SIM_WARNINGS=@sim_warnings@ +SIM_ENDIAN=@sim_endian@ +SIM_HOSTENDIAN=@sim_hostendian@ +SIM_INLINE=@sim_inline@ +SIM_RESERVED_BITS=@sim_reserved_bits@ + +SIM_EXTRA_CFLAGS = \ + $(SIM_WARNINGS) \ + $(SIM_ENDIAN) \ + $(SIM_HOSTENDIAN) \ + $(SIM_INLINE) \ + $(SIM_RESERVED_BITS) \ + -DWITH_TARGET_WORD_MSB=31 + +# List of main object files for `run'. +SIM_RUN_OBJS = nrun.o + +# Dependency of `clean' to clean any extra files. +SIM_EXTRA_CLEAN = clean-igen + + +## COMMON_POST_CONFIG_FRAG + +# Rules need to build $(SIM_OBJS), plus whatever else the target wants. + +# ... target specific rules ... + +BUILT_SRC_FROM_IGEN = \ + icache.h \ + icache.c \ + idecode.h \ + idecode.c \ + semantics.h \ + semantics.c \ + model.h \ + model.c \ + support.h \ + support.c \ + itable.h itable.c +$(BUILT_SRC_FROM_IGEN): tmp-igen +# + +.PHONY: clean-igen +clean-igen: + rm -f $(BUILT_SRC_FROM_IGEN) + rm -f tmp-igen tmp-insns + +../igen/igen: + cd ../igen && $(MAKE) + +tmp-igen: $(srcdir)/dc $(srcdir)/insns $(srcdir)/ic ../igen/igen + cd ../igen && $(MAKE) + @echo "Generating short version ..." + ../igen/igen \ + -G direct-access \ + -G delayed-branch \ + -G omit-line-numbers \ + -F short,emul \ + -B 32 -H 31 \ + -o $(srcdir)/dc \ + -k $(srcdir)/ic \ + -i $(srcdir)/insns \ + -n icache.h -hc tmp-icache.h \ + -n icache.c -c tmp-icache.c \ + -n semantics.h -hs tmp-semantics.h \ + -n semantics.c -s tmp-semantics.c \ + -n idecode.h -hd tmp-idecode.h \ + -n idecode.c -d tmp-idecode.c \ + -n model.h -hm tmp-model.h \ + -n model.c -m tmp-model.c \ + -n support.h -hf tmp-support.h \ + -n support.c -f tmp-support.c \ + -n itable.h -ht tmp-itable.h \ + -n itable.c -t tmp-itable.c + $(srcdir)/../../move-if-change tmp-icache.h icache.h + $(srcdir)/../../move-if-change tmp-icache.c icache.c + $(srcdir)/../../move-if-change tmp-idecode.h idecode.h + $(srcdir)/../../move-if-change tmp-idecode.c idecode.c + $(srcdir)/../../move-if-change tmp-semantics.h semantics.h + $(srcdir)/../../move-if-change tmp-semantics.c semantics.c + $(srcdir)/../../move-if-change tmp-model.h model.h + $(srcdir)/../../move-if-change tmp-model.c model.c + $(srcdir)/../../move-if-change tmp-support.h support.h + $(srcdir)/../../move-if-change tmp-support.c support.c + $(srcdir)/../../move-if-change tmp-itable.h itable.h + $(srcdir)/../../move-if-change tmp-itable.c itable.c + touch tmp-igen + +ENGINE_H = \ + sim-main.h \ + $(srcdir)/../common/sim-basics.h \ + config.h \ + $(srcdir)/../common/sim-config.h \ + $(srcdir)/../common/sim-inline.h \ + $(srcdir)/../common/sim-types.h \ + $(srcdir)/../common/sim-bits.h \ + $(srcdir)/../common/sim-endian.h \ + itable.h \ + idecode.h \ + cpu.h \ + alu.h \ + $(srcdir)/../common/sim-alu.h \ + $(srcdir)/../common/sim-core.h \ + $(srcdir)/../common/sim-events.h \ + +idecode.o: $(ENGINE_H) +semantics.o: $(ENGINE_H) +interp.o: interp.c $(ENGINE_H) +sim-calls.o: sim-calls.c $(ENGINE_H) +cpu.o: cpu.c $(ENGINE_H) |