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| author | Andrew Cagney <cagney@redhat.com> | 1997-09-04 03:47:39 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-09-04 03:47:39 +0000 |
| commit | a34abff813f4fdd5f289ea45de9e874e31e7edf3 (patch) | |
| tree | f6d3be383893c3adaae166e570d5eccd71f08427 /sim/tic80/ChangeLog | |
| parent | 600d83316cfa68f72666d792244890789812b51a (diff) | |
| download | gdb-a34abff813f4fdd5f289ea45de9e874e31e7edf3.zip gdb-a34abff813f4fdd5f289ea45de9e874e31e7edf3.tar.gz gdb-a34abff813f4fdd5f289ea45de9e874e31e7edf3.tar.bz2 | |
o Add modulo argument to sim_core_attach
o Add sim-memopt module - memory option processing.
Diffstat (limited to 'sim/tic80/ChangeLog')
| -rw-r--r-- | sim/tic80/ChangeLog | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index 0ac08b2..6a5102b 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,14 @@ +Thu Sep 4 10:48:57 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_open): Use sim_do_command to add memory, only + add memory if none already present. + (sim_open): Move init of registers from here. + (sim_create_inferior): To here. Init modules. + + * Makefile.in (SIM_OBJS): Add sim-memopt.o module. + + * sim-calls.c (sim_open): Add zero modulo arg to sim_core_attach. + Mon Sep 1 11:06:30 1997 Andrew Cagney <cagney@b1.cygnus.com> * sim-calls.c (sim_open): Use sim_state_alloc |