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| author | Andrew Cagney <cagney@redhat.com> | 1997-05-27 06:48:20 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-27 06:48:20 +0000 |
| commit | 2f2e6c5d5bf76a01caa0d2da27ac21e45ee2276e (patch) | |
| tree | e423d11adc8c988ab292d78c6e7a592064ac5ead /sim/tic80/ChangeLog | |
| parent | d82e4bf6cc9f6dfb853b2c9fa138b3640381fdf6 (diff) | |
| download | gdb-2f2e6c5d5bf76a01caa0d2da27ac21e45ee2276e.zip gdb-2f2e6c5d5bf76a01caa0d2da27ac21e45ee2276e.tar.gz gdb-2f2e6c5d5bf76a01caa0d2da27ac21e45ee2276e.tar.bz2 | |
Extend xor-endian and per-cpu support in core module.
Allow negated test when watching value within core.
Diffstat (limited to 'sim/tic80/ChangeLog')
| -rw-r--r-- | sim/tic80/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index b6fdd6f..d0c56c0 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,8 @@ +Tue May 27 13:22:13 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_read): Pass NULL cpu to sim_core_read_buffer. + (sim_write): Ditto for write. + Tue May 20 09:33:31 1997 Andrew Cagney <cagney@b1.cygnus.com> * sim-calls.c (sim_load): Set STATE_LOADED_P. |