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| author | Andrew Cagney <cagney@redhat.com> | 1997-05-07 13:58:52 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-07 13:58:52 +0000 |
| commit | 381f42ef5d76943fb09494130c95abfb9b70e024 (patch) | |
| tree | f45512a238920ab0e21b11e3efdb62d924984c9d /sim/tic80/ChangeLog | |
| parent | bd3274c6d9a56ad8cafa149fd72f0a0cc1a6d0fc (diff) | |
| download | gdb-381f42ef5d76943fb09494130c95abfb9b70e024.zip gdb-381f42ef5d76943fb09494130c95abfb9b70e024.tar.gz gdb-381f42ef5d76943fb09494130c95abfb9b70e024.tar.bz2 | |
o Clean-up tic80 fp tracing
o Fill in more tic80 insns
Diffstat (limited to 'sim/tic80/ChangeLog')
| -rw-r--r-- | sim/tic80/ChangeLog | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index fa14ec9..60761ce 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,32 @@ +Wed May 7 11:48:55 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add. + * insn: Clean up fpu tracing. + + * sim-calls.c (sim_create_inferior): Start out with interrupts + enabled. + + * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument + sink + + * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement. + + * insns (do_*): Remove MY_INDEX/indx argument from support functions, + igen now handles this. + + * cpu.h (CR): New macro - access TIc80 control registers. + + * misc.c: New file. + (tic80_cr2index): New function, map control register opcode index + into the internal CR enum. + + * interp.c + (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from + here + * misc.c: to here. + + * Makefile.in (SIM_OBJS): Add misc.o. + Tue May 6 15:22:58 1997 Mike Meissner <meissner@cygnus.com> * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on |