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author | Michael Meissner <gnu@the-meissners.org> | 1997-05-11 14:32:32 +0000 |
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committer | Michael Meissner <gnu@the-meissners.org> | 1997-05-11 14:32:32 +0000 |
commit | 450be2349aa1beda81274be407713657f457ef50 (patch) | |
tree | fe98ee6fdf24fbef51e70df9717e9669aaf548ff /sim/tic80/ChangeLog | |
parent | 20b2f9bc83913de6065a40c14c7cb7c96e7bb8d1 (diff) | |
download | gdb-450be2349aa1beda81274be407713657f457ef50.zip gdb-450be2349aa1beda81274be407713657f457ef50.tar.gz gdb-450be2349aa1beda81274be407713657f457ef50.tar.bz2 |
Fix shift/lmo insns; Subu does arithmetic unsigned
Diffstat (limited to 'sim/tic80/ChangeLog')
-rw-r--r-- | sim/tic80/ChangeLog | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index 382fa79..b22b9d3 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,17 @@ +Sun May 11 10:25:14 1997 Michael Meissner <meissner@cygnus.com> + + * cpu.h (tic80_trace_shift): Add declaration. + (TRACE_SHIFT): New macro to trace shift instructions. + + * misc.c (tic80_trace_alu2): Align spacing. + (tic80_trace_shift): New function to trace shifts. + + * insns (lmo): Add missing 0b prefix to bits. + (do_shift): Use ~ (unsigned32)0, instead of -1. Use TRACE_SHIFT + instead of TRACE_ALU2. + (sl r): Use EndMask as is, instead of using Source+1 register. + (subu): Operands are unsigned, not signed. + Sat May 10 12:35:47 1997 Michael Meissner <meissner@cygnus.com> * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not |