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| author | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
| commit | 37a684b84d5c722848ebdc7203052d65c6b35e30 (patch) | |
| tree | 3d7fa5b15efab746e9b8cc87449fa8664b6ed359 /sim/tic80/ChangeLog | |
| parent | 77bd8dfa1f3678ea3c3d05f40de29a36802d21f5 (diff) | |
| download | gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.zip gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.gz gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.bz2 | |
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
Diffstat (limited to 'sim/tic80/ChangeLog')
| -rw-r--r-- | sim/tic80/ChangeLog | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index 8f9ffd0..81a7ad3 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,20 @@ +Fri May 16 11:57:49 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * ic (compute): Drop check for REG == 0, now always forced to + zero. + + * cpu.h (GPR_SET): New macro update the gpr. + * insns (do_add): Use GPR_SET to update the GPR register. + + * sim-calls.c (sim_fetch_register): Pretend that r0 is zero. + + * Makefile.in (tmp-igen): Specify zero-r0 so that every + instruction clears r0. + + * interp.c (engine_run_until_stop): Igen now generates code to + clear r0. + (engine_step): Ditto. + Thu May 15 11:45:37 1997 Andrew Cagney <cagney@b1.cygnus.com> * insns (do_shift): When rot==0 and zero/sign merge treat it as |