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author | Andrew Cagney <cagney@redhat.com> | 1997-05-15 02:21:11 +0000 |
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committer | Andrew Cagney <cagney@redhat.com> | 1997-05-15 02:21:11 +0000 |
commit | aa3a044769b6cc60d1505aedd70c2776fb4f42be (patch) | |
tree | b43d0ca5bb0288b8c546e49041db1956f7dc8eaf /sim/tic80/ChangeLog | |
parent | 2310e3c2b5591bfe2459bf6fb36c4ae147c94982 (diff) | |
download | gdb-aa3a044769b6cc60d1505aedd70c2776fb4f42be.zip gdb-aa3a044769b6cc60d1505aedd70c2776fb4f42be.tar.gz gdb-aa3a044769b6cc60d1505aedd70c2776fb4f42be.tar.bz2 |
Fix double conversion problem.
Diffstat (limited to 'sim/tic80/ChangeLog')
-rw-r--r-- | sim/tic80/ChangeLog | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index ea9bb67..89ebd48 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,4 +1,17 @@ -Thu May 15 10:14:06 1997 Andrew Cagney <cagney@b1.cygnus.com> +Thu May 15 11:45:37 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * insns (get_fp_reg): Use sim_fpu_u32to to perform unsigned + conversion. + (do_fcmp): Update to use new fp compare functions. Make reg nr arg + instead of reg. Stops fp overflow. + (get_fp_reg): Assume val is valid when reg == 0. + (set_fp_reg): Fix double conversion. + + * misc.c (tic80_trace_fpu1): New function, trace simple fp op. + + * insns (do_frnd): Add tracing. + + * cpu.h (TRACE_FPU1): Ditto. * insns (do_trap): Printf formatting. |