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| author | Michael Meissner <gnu@the-meissners.org> | 1998-02-17 19:38:48 +0000 |
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| committer | Michael Meissner <gnu@the-meissners.org> | 1998-02-17 19:38:48 +0000 |
| commit | 9902213101350fc9ad9386879e28aee7895feae8 (patch) | |
| tree | c273d25dfc4a116629124885e7b73c1605d63ccb /sim/tic80/ChangeLog | |
| parent | 5290378abc09ab96d8a25be05c07bcfc1b23caab (diff) | |
| download | gdb-9902213101350fc9ad9386879e28aee7895feae8.zip gdb-9902213101350fc9ad9386879e28aee7895feae8.tar.gz gdb-9902213101350fc9ad9386879e28aee7895feae8.tar.bz2 | |
Better tracing for conditional branches
Diffstat (limited to 'sim/tic80/ChangeLog')
| -rw-r--r-- | sim/tic80/ChangeLog | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index 3c2258a..cd494e5 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,13 @@ +Tue Feb 17 14:35:05 1998 Michael Meissner <meissner@cygnus.com> + + * misc.c (tic80_trace_cond_br): Take size/code arguments, and + decode bcond conditions and bbo/bbz comparison bits. + + * cpu.h (tic80_trace_cond_br): Update prototype. + (TRACE_COND_PR): Take size/code additional arguments. + + * insns: (bbo/bbz/bcnd): Update call to TRACE_COND_PR. + Tue Feb 17 12:50:27 1998 Andrew Cagney <cagney@b1.cygnus.com> * sim-calls.c (sim_store_register, sim_fetch_register): Pass in |