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| author | Jim Wilson <jim.wilson@linaro.org> | 2017-04-08 12:06:31 -0700 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2017-04-08 12:08:20 -0700 |
| commit | b630840c9c22a877b2c6270880a214f7b451f546 (patch) | |
| tree | b3382832c450a81d5a25dd52703e7db7c3863411 /sim/testsuite | |
| parent | ae27d3fe76ffb54e7d413a67d8c8d76ca78a9681 (diff) | |
| download | gdb-b630840c9c22a877b2c6270880a214f7b451f546.zip gdb-b630840c9c22a877b2c6270880a214f7b451f546.tar.gz gdb-b630840c9c22a877b2c6270880a214f7b451f546.tar.bz2 | |
Add support for fcvtl and fcvtl2.
sim/aarch64/
* simulator.c (do_vec_FCVTL): New.
(do_vec_op1): Call do_vec_FCVTL.
sim/testsuite/sim/aarch64/
* fcvtl.s: New.
Diffstat (limited to 'sim/testsuite')
| -rw-r--r-- | sim/testsuite/sim/aarch64/ChangeLog | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/aarch64/fcvtl.s | 59 |
2 files changed, 61 insertions, 0 deletions
diff --git a/sim/testsuite/sim/aarch64/ChangeLog b/sim/testsuite/sim/aarch64/ChangeLog index 5aaa67f..cf0da6d 100644 --- a/sim/testsuite/sim/aarch64/ChangeLog +++ b/sim/testsuite/sim/aarch64/ChangeLog @@ -1,5 +1,7 @@ 2017-04-08 Jim Wilson <jim.wilson@linaro.org> + * fcvtl.s: New. + * fcmXX.s: New. 2017-03-25 Jim Wilson <jim.wilson@linaro.org> diff --git a/sim/testsuite/sim/aarch64/fcvtl.s b/sim/testsuite/sim/aarch64/fcvtl.s new file mode 100644 index 0000000..8febc08 --- /dev/null +++ b/sim/testsuite/sim/aarch64/fcvtl.s @@ -0,0 +1,59 @@ +# mach: aarch64 + +# Check the FP convert to longer precision: fcvtl, fcvtl2. +# Test values 1.5, -1.5, INTMAX, and INT_MIN. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 1069547520 + .word 3217031168 + .word 1325400064 + .word 3472883712 +d1p5: + .word 0 + .word 1073217536 +dm1p5: + .word 0 + .word -1074266112 +dimax: + .word 0 + .word 1105199104 +dimin: + .word 0 + .word -1042284544 + + start + adrp x0, input + add x0, x0, #:lo12:input + ld1 {v0.4s}, [x0] + + fcvtl v1.2d, v0.2s + mov x1, v1.d[0] + adrp x2, d1p5 + ldr x3, [x2, #:lo12:d1p5] + cmp x1, x3 + bne .Lfailure + mov x1, v1.d[1] + adrp x2, dm1p5 + ldr x3, [x2, #:lo12:dm1p5] + cmp x1, x3 + bne .Lfailure + + fcvtl2 v2.2d, v0.4s + mov x1, v2.d[0] + adrp x2, dimax + ldr x3, [x2, #:lo12:dimax] + cmp x1, x3 + bne .Lfailure + mov x1, v2.d[1] + adrp x2, dimin + ldr x3, [x2, #:lo12:dimin] + cmp x1, x3 + bne .Lfailure + + pass +.Lfailure: + fail |