sim: example-synacor: a simple implementation for reference

Provide a simple example simulator for people porting to new targets
to use as a reference.  This one has the advantage of being used by
people and having a fun program available for it.

It doesn't require a special target -- the example simulators can be
built for any existing port.

20 files changed, 429 insertions, 0 deletions

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 4160911..b9efa92 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,5 +1,9 @@
 2021-04-03  Mike Frysinger  <vapier@gentoo.org>
 
+	* lib/sim-defs.exp (run_sim_test): Convert examples to binaries.
+
+2021-04-03  Mike Frysinger  <vapier@gentoo.org>
+
 	* local.mk: Include %D%/common/local.mk.
 	* common/Makefile.in: Removed.
 	* common/local.mk: New file.
diff --git a/sim/testsuite/example-synacor/ChangeLog b/sim/testsuite/example-synacor/ChangeLog
new file mode 100644
index 0000000..5d45621
--- /dev/null
+++ b/sim/testsuite/example-synacor/ChangeLog
@@ -0,0 +1,5 @@
+2021-04-03  Mike Frysinger  <vapier@gentoo.org>
+
+	* add.s, allinsn.exp, and.s, call.s, exit-0.s, gt.s, isa.inc, jmp.s,
+	mem.s, mod.s, mult.s, not.s, or.s, push-pop.s, ret.s, set.s,
+	testutils.inc: New files.
diff --git a/sim/testsuite/example-synacor/add.s b/sim/testsuite/example-synacor/add.s
new file mode 100644
index 0000000..64a8c20
--- /dev/null
+++ b/sim/testsuite/example-synacor/add.s
@@ -0,0 +1,24 @@
+# check the ADD insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+
+	SET r2, 2
+	ADD r2, r2, r2
+	EQ r3, r2, 4
+	JF r3, 2
+
+	ADD r1, 100, r2
+	EQ r4, r1, 104
+	JF r4, 2
+
+	# 0x7ffe == -2
+	ADD r0, r1, 0x7ffe
+	EQ r4, r0, 102
+	JF r4, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/allinsn.exp b/sim/testsuite/example-synacor/allinsn.exp
new file mode 100644
index 0000000..7210a61
--- /dev/null
+++ b/sim/testsuite/example-synacor/allinsn.exp
@@ -0,0 +1,19 @@
+# Example synacor simulator testsuite.
+
+if [istarget *] {
+    # Used to locate the `run` program.
+    global arch
+    set arch "example-synacor"
+
+    # All machines.
+    set all_machs "example"
+
+    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
+	# If we're only testing specific files and this isn't one of them,
+	# skip it.
+	if ![runtest_file_p $runtests $src] {
+	    continue
+	}
+	run_sim_test $src $all_machs
+    }
+}
diff --git a/sim/testsuite/example-synacor/and.s b/sim/testsuite/example-synacor/and.s
new file mode 100644
index 0000000..1d18859
--- /dev/null
+++ b/sim/testsuite/example-synacor/and.s
@@ -0,0 +1,18 @@
+# check the AND insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+
+	AND r2, 0xfff, 0x7f0c
+	EQ r3, r2, 0xf0c
+	JF r3, 2
+
+	AND r2, r2, 0xf
+	EQ r3, r2, 0xc
+	JF r3, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/call.s b/sim/testsuite/example-synacor/call.s
new file mode 100644
index 0000000..6d7b545
--- /dev/null
+++ b/sim/testsuite/example-synacor/call.s
@@ -0,0 +1,14 @@
+# check the CALL insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	CALL 3
+	HALT
+
+	POP r0
+	EQ r1, r0, 2
+	JF r1, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/exit-0.s b/sim/testsuite/example-synacor/exit-0.s
new file mode 100644
index 0000000..2c1fb72
--- /dev/null
+++ b/sim/testsuite/example-synacor/exit-0.s
@@ -0,0 +1,10 @@
+# check that the sim doesn't die immediately.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	NOOP
+	NOOP
+	NOOP
+	pass
diff --git a/sim/testsuite/example-synacor/gt.s b/sim/testsuite/example-synacor/gt.s
new file mode 100644
index 0000000..aef28e3
--- /dev/null
+++ b/sim/testsuite/example-synacor/gt.s
@@ -0,0 +1,31 @@
+# check the GT insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+
+	GT r0, 3, 2
+	EQ r1, r0, 1
+	JF r1, 2
+
+	GT r0, 2, 2
+	EQ r1, r0, 0
+	JF r1, 2
+
+	GT r0, 1, 2
+	EQ r1, r0, 0
+	JF r1, 2
+
+	SET r2, 3
+	SET r3, 4
+	GT r0, r2, r3
+	EQ r1, r0, 0
+	JF r1, 2
+	GT r0, r3, r2
+	EQ r1, r0, 1
+	JF r1, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/isa.inc b/sim/testsuite/example-synacor/isa.inc
new file mode 100644
index 0000000..e2e1136
--- /dev/null
+++ b/sim/testsuite/example-synacor/isa.inc
@@ -0,0 +1,108 @@
+# Macros for the fake ISA.  Keep in sync with example-synacor/README.arch-spec.
+
+# These .set macros will generate symbols in the output ELF, but it also allows
+# use to use them as arguments to the insns below.  Oh well.
+.set r0, 32768
+.set r1, r0+1
+.set r2, r0+2
+.set r3, r0+3
+.set r4, r0+4
+.set r5, r0+5
+.set r6, r0+6
+.set r7, r0+7
+
+# The target is little endian, so make sure we output the 16-bit words as such.
+.macro _op op:req, more:vararg
+	.byte \op & 0xff, (\op >> 8) & 0xff
+	.ifnb \more
+	_op \more
+	.endif
+.endm
+
+.macro HALT
+	_op 0
+.endm
+
+.macro SET a:req, b:req
+	_op 1, \a, \b
+.endm
+
+.macro PUSH a:req
+	_op 2, \a
+.endm
+
+.macro POP a:req
+	_op 3, \a
+.endm
+
+.macro EQ a:req, b:req, c:req
+	_op 4, \a, \b, \c
+.endm
+
+.macro GT a:req, b:req, c:req
+	_op 5, \a, \b, \c
+.endm
+
+.macro JMP a:req
+	_op 6, \a
+.endm
+
+.macro JT a:req, b:req
+	_op 7, \a, \b
+.endm
+
+.macro JF a:req, b:req
+	_op 8, \a, \b
+.endm
+
+.macro ADD a:req, b:req, c:req
+	_op 9, \a, \b, \c
+.endm
+
+.macro MULT a:req, b:req, c:req
+	_op 10, \a, \b, \c
+.endm
+
+.macro MOD a:req, b:req, c:req
+	_op 11, \a, \b, \c
+.endm
+
+.macro AND a:req, b:req, c:req
+	_op 12, \a, \b, \c
+.endm
+
+.macro OR a:req, b:req, c:req
+	_op 13, \a, \b, \c
+.endm
+
+.macro NOT a:req, b:req
+	_op 14, \a, \b
+.endm
+
+.macro RMEM a:req, b:req
+	_op 15, \a, \b
+.endm
+
+.macro WMEM a:req, b:req
+	_op 16, \a, \b
+.endm
+
+.macro CALL a:req
+	_op 17, \a
+.endm
+
+.macro RET
+	_op 18
+.endm
+
+.macro OUT a:req
+	_op 19, \a
+.endm
+
+.macro IN a:req
+	_op 20, \a
+.endm
+
+.macro NOOP
+	_op 21
+.endm
diff --git a/sim/testsuite/example-synacor/jmp.s b/sim/testsuite/example-synacor/jmp.s
new file mode 100644
index 0000000..dcacf66
--- /dev/null
+++ b/sim/testsuite/example-synacor/jmp.s
@@ -0,0 +1,9 @@
+# check the JMP insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+	pass
diff --git a/sim/testsuite/example-synacor/mem.s b/sim/testsuite/example-synacor/mem.s
new file mode 100644
index 0000000..24aa0a9
--- /dev/null
+++ b/sim/testsuite/example-synacor/mem.s
@@ -0,0 +1,25 @@
+# check the RMEM & WMEM insns.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 14
+	HALT
+	pass
+
+	# Read a constant address.
+	RMEM r0, 1
+	EQ r1, r0, 14
+	JF r1, 2
+
+	# Change the first JMP to skip HALT and hit the pass.
+	WMEM 1, 3
+
+	# Read an address in a register.
+	SET r2, 1
+	RMEM r0, r2
+	EQ r1, r0, 3
+	JF r1, 2
+
+	JMP 0
diff --git a/sim/testsuite/example-synacor/mod.s b/sim/testsuite/example-synacor/mod.s
new file mode 100644
index 0000000..f0b4217
--- /dev/null
+++ b/sim/testsuite/example-synacor/mod.s
@@ -0,0 +1,18 @@
+# check the MOD insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+
+	MOD r0, 8, 3
+	EQ r1, r0, 2
+	JF r1, 2
+
+	MOD r0, r0, 2
+	EQ r1, r0, 0
+	JF r1, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/mult.s b/sim/testsuite/example-synacor/mult.s
new file mode 100644
index 0000000..d323cf5
--- /dev/null
+++ b/sim/testsuite/example-synacor/mult.s
@@ -0,0 +1,18 @@
+# check the MULT insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+
+	MULT r0, 3, 2
+	EQ r1, r0, 6
+	JF r1, 2
+
+	MULT r0, r0, 8
+	EQ r1, r0, 48
+	JF r1, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/not.s b/sim/testsuite/example-synacor/not.s
new file mode 100644
index 0000000..8a4a570
--- /dev/null
+++ b/sim/testsuite/example-synacor/not.s
@@ -0,0 +1,15 @@
+# check the NOT insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+
+	SET r2, 0xc
+	NOT r0, r2
+	EQ r3, r0, 0x7ff3
+	JF r3, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/or.s b/sim/testsuite/example-synacor/or.s
new file mode 100644
index 0000000..f8f2ae3
--- /dev/null
+++ b/sim/testsuite/example-synacor/or.s
@@ -0,0 +1,18 @@
+# check the OR insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+
+	OR r2, 0xf, 0x80
+	EQ r3, r2, 0x8f
+	JF r3, 2
+
+	OR r2, r2, 0xff
+	EQ r3, r2, 0xff
+	JF r3, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/push-pop.s b/sim/testsuite/example-synacor/push-pop.s
new file mode 100644
index 0000000..b8199c5
--- /dev/null
+++ b/sim/testsuite/example-synacor/push-pop.s
@@ -0,0 +1,22 @@
+# check the PUSH & POP insns.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+
+	PUSH 1
+	SET r0, 3
+	PUSH r0
+	POP r1
+	POP r2
+	EQ r7, r0, 3
+	JF r7, 2
+	EQ r7, r1, 3
+	JF r7, 2
+	EQ r7, r2, 1
+	JF r7, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/ret.s b/sim/testsuite/example-synacor/ret.s
new file mode 100644
index 0000000..63bfa71
--- /dev/null
+++ b/sim/testsuite/example-synacor/ret.s
@@ -0,0 +1,13 @@
+# check the RET insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 13
+	pass
+
+	SET r5, 2
+	PUSH r5
+	RET
+	HALT
diff --git a/sim/testsuite/example-synacor/set.s b/sim/testsuite/example-synacor/set.s
new file mode 100644
index 0000000..8b441c7
--- /dev/null
+++ b/sim/testsuite/example-synacor/set.s
@@ -0,0 +1,20 @@
+# check the SET insn.
+# mach: example
+
+.include "testutils.inc"
+
+	start
+	JMP 3
+	HALT
+
+	SET r2, 2
+	EQ r3, r2, 2
+	JF r3, 2
+	SET r1, 1
+	EQ r3, r1, 1
+	JF r3, 2
+	SET r0, r2
+	EQ r3, r0, 2
+	JF r3, 2
+
+	pass
diff --git a/sim/testsuite/example-synacor/testutils.inc b/sim/testsuite/example-synacor/testutils.inc
new file mode 100644
index 0000000..0f286c6
--- /dev/null
+++ b/sim/testsuite/example-synacor/testutils.inc
@@ -0,0 +1,31 @@
+.include "isa.inc"
+
+# MACRO: pass
+# Write 'pass' to stdout and quit
+	.macro pass
+	OUT 'p'
+	OUT 'a'
+	OUT 's'
+	OUT 's'
+	OUT '\n'
+	HALT
+	.endm
+
+# MACRO: fail
+# Write 'fail' to stdout and quit
+	.macro fail
+	OUT 'f'
+	OUT 'a'
+	OUT 'i'
+	OUT 'l'
+	OUT '\n'
+	HALT
+	.endm
+
+# MACRO: start
+# All assembler tests should start with a call to "start"
+	.macro start
+	.text
+.global _start
+_start:
+	.endm
diff --git a/sim/testsuite/lib/sim-defs.exp b/sim/testsuite/lib/sim-defs.exp
index 0157f9b..e1254a3 100644
--- a/sim/testsuite/lib/sim-defs.exp
+++ b/sim/testsuite/lib/sim-defs.exp
@@ -378,6 +378,13 @@ proc run_sim_test { name requested_machs } {
 	    set options "$options timeout=$opts(timeout)"
 	}
 
+	if [string match "example" "$mach"] {
+	    set objcopy [find_binutils_prog objcopy]
+	    set comp_output [remote_exec host $objcopy "-O binary -j .text ${name}.x ${name}.bin"]
+	    file rename -force "${name}.bin" "${name}.x"
+	    append opts(sim,$mach) " --target binary"
+	}
+
 	set result [sim_run ${name}.x "$opts(sim,$mach) $global_sim_options" "$opts(progopts)" "" "$options"]
 	set return_code [lindex $result 0]
 	set output [lindex $result 1]