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| author | Jeff Law <jeffreyalaw@gmail.com> | 2022-03-29 20:05:51 -0400 |
|---|---|---|
| committer | Jeff Law <jeffreyalaw@gmail.com> | 2022-03-29 20:08:35 -0400 |
| commit | 5321c31bc78379a33f07dc7bef9256d05b942ad7 (patch) | |
| tree | 6b645d1443adc5e72097b29fec1a9f584c60b6a7 /sim/testsuite | |
| parent | c09115ad6e3531be5fc779098a093605622b161e (diff) | |
| download | gdb-5321c31bc78379a33f07dc7bef9256d05b942ad7.zip gdb-5321c31bc78379a33f07dc7bef9256d05b942ad7.tar.gz gdb-5321c31bc78379a33f07dc7bef9256d05b942ad7.tar.bz2 | |
Fix for MUL instruction on the v850
* sim/v850/simops.c (Multiply64): Properly test if we need to
negate either of the operands.
* sim/testsuite/v850/mul.cgs: New test.
Diffstat (limited to 'sim/testsuite')
| -rw-r--r-- | sim/testsuite/v850/mul.cgs | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/sim/testsuite/v850/mul.cgs b/sim/testsuite/v850/mul.cgs new file mode 100644 index 0000000..7d19b70 --- /dev/null +++ b/sim/testsuite/v850/mul.cgs @@ -0,0 +1,15 @@ +# v850e mul +# mach: v850e +# as(v850e): -mv850e + + .include "testutils.inc" + +# Trivial regression test for incorrect sign bit handling in mul + + seti -10, r1 + seti 2, r2 + mul r1, r2, r3 + reg r2, -20 + reg r3, -1 + + pass |