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authorAndrew Bennett <andrew.bennett@imgtec.com>2015-09-25 15:52:18 +0100
committerAndrew Bennett <andrew.bennett@imgtec.com>2015-09-25 15:52:18 +0100
commit8e394ffc7ab691eafcf276d7ae578454a8c5548f (patch)
tree309466c282f5b0adc8a27e5f8fa3b6a6f2e64ee0 /sim/testsuite
parent8a9e7a9121490a8c64d8c17f5be510e43104f6d9 (diff)
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[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> Ali Lown <ali.lown@imgtec.com> sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips.
Diffstat (limited to 'sim/testsuite')
-rw-r--r--sim/testsuite/sim/mips/ChangeLog11
-rw-r--r--sim/testsuite/sim/mips/basic.exp29
-rw-r--r--sim/testsuite/sim/mips/hilo-hazard-4.s37
-rw-r--r--sim/testsuite/sim/mips/testutils.inc6
4 files changed, 77 insertions, 6 deletions
diff --git a/sim/testsuite/sim/mips/ChangeLog b/sim/testsuite/sim/mips/ChangeLog
index e5913c1..ada4e4c 100644
--- a/sim/testsuite/sim/mips/ChangeLog
+++ b/sim/testsuite/sim/mips/ChangeLog
@@ -1,3 +1,14 @@
+2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
+ Ali Lown <ali.lown@imgtec.com>
+
+ * basic.exp (run_micromips_test, run_sim_tests): New functions
+ Add support for micromips tests.
+ * hilo-hazard-4.s: New file.
+ * testutils.inc (_dowrite): Changed reserved instruction encoding.
+ (writemsg): Moved the la and li instructions before the data they are
+ assigned to, which prevents a bug where MIPS32 relocations are used
+ instead of micromips relocations when building for micromips.
+
2015-04-13 Hans-Peter Nilsson <hp@axis.com>
* basic.exp: Don't unset target ldscript here.
diff --git a/sim/testsuite/sim/mips/basic.exp b/sim/testsuite/sim/mips/basic.exp
index ddef535..f810741 100644
--- a/sim/testsuite/sim/mips/basic.exp
+++ b/sim/testsuite/sim/mips/basic.exp
@@ -25,12 +25,28 @@ proc run_hilo_test {testfile models nops} {
}
}
+# Runs micromips tests by adding -mmicromips to as options
+proc run_micromips_test { name requested_machs } {
+ global global_as_options;
+ set gas_old $global_as_options;
+ append global_as_options " -mmicromips "
+ run_sim_test $name $requested_machs
+ set global_as_options $gas_old
+}
+
+# Runs all specified tests
+proc run_sim_tests { name requested_machs { requested_micromips_machs "" } } {
+ run_sim_test $name $requested_machs
+ run_micromips_test $name $requested_micromips_machs
+}
# Only test mips*-*-elf (e.g., no mips*-*-linux)
if {[istarget mips*-*-elf]} {
set dspmodels ""
set mdmxmodels ""
+ set micromipsmodels ""
+ set micromipsdspmodels ""
if {[istarget mipsisa64sb1*-*-elf]} {
set models "sb1"
@@ -46,11 +62,15 @@ if {[istarget mips*-*-elf]} {
set submodels ""
append dspmodels " mips32r2 mips64r2"
append mdmxmodels " mips64 mips32r2 mips64r2"
+ append micromipsmodels " mips32r2"
+ append micromipsdspmodels " mips32r2 mips64r2"
} elseif {[istarget mipsisa32*-*-elf]} {
set models "mips32 mips32r2"
set submodels "mips1 mips2"
append dspmodels " mips32r2"
append mdmxmodels " mips32r2"
+ append micromipsmodels " mips32r2"
+ append micromipsdspmodels " mips32r2"
} elseif {[istarget mips64vr*-*-elf]} {
set models "vr4100 vr4111 vr4120 vr5000 vr5400 vr5500"
set submodels "mips1 mips2 mips3 mips4"
@@ -65,12 +85,14 @@ if {[istarget mips*-*-elf]} {
append submodels " " $models
set cpu_option -march
- run_sim_test sanity.s $submodels
+ run_sim_tests sanity.s $submodels $micromipsmodels
+
foreach nops {0 1} {
run_hilo_test hilo-hazard-1.s $models $nops
run_hilo_test hilo-hazard-2.s $models $nops
}
run_hilo_test hilo-hazard-3.s $models 2
+ run_hilo_test hilo-hazard-4.s $micromipsmodels 2
run_sim_test fpu64-ps.s $submodels
run_sim_test fpu64-ps-sb1.s $submodels
@@ -78,6 +100,7 @@ if {[istarget mips*-*-elf]} {
run_sim_test mdmx-ob.s $mdmxmodels
run_sim_test mdmx-ob-sb1.s $mdmxmodels
- run_sim_test mips32-dsp.s $dspmodels
- run_sim_test mips32-dsp2.s $dspmodels
+ run_sim_tests mips32-dsp.s $dspmodels $micromipsdspmodels
+ run_sim_tests mips32-dsp2.s $dspmodels $micromipsdspmodels
+
}
diff --git a/sim/testsuite/sim/mips/hilo-hazard-4.s b/sim/testsuite/sim/mips/hilo-hazard-4.s
new file mode 100644
index 0000000..e83fbfa
--- /dev/null
+++ b/sim/testsuite/sim/mips/hilo-hazard-4.s
@@ -0,0 +1,37 @@
+# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
+#
+# mach: all
+# as: -mabi=eabi -mmicromips
+# ld: -N -Ttext=0x80010000
+# output: pass\\n
+
+# Copyright (C) 2013-2015 Imagination Technologies, Ltd.
+# All rights reserved.
+# Contributed by Andrew Bennett (andrew.bennett@imgtec.com)
+#
+# This file is part of the MIPS sim.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, see <http://www.gnu.org/licenses/>.
+
+ .include "hilo-hazard.inc"
+ .include "testutils.inc"
+
+ setup
+
+ .set noreorder
+ .ent DIAG
+DIAG:
+ hilo
+ pass
+ .end DIAG
diff --git a/sim/testsuite/sim/mips/testutils.inc b/sim/testsuite/sim/mips/testutils.inc
index 6ea59f0..0029fc0 100644
--- a/sim/testsuite/sim/mips/testutils.inc
+++ b/sim/testsuite/sim/mips/testutils.inc
@@ -21,12 +21,12 @@
# $1, $4, $5, %6, are used as temps by the macros defined here.
.macro writemsg msg
+ la $5, 901f
+ li $6, 902f - 901f
.data
901: .ascii "\msg\n"
902:
.previous
- la $5, 901b
- li $6, 902b - 901b
.set push
.set noreorder
jal _dowrite
@@ -81,7 +81,7 @@ _pass:
_dowrite:
# Write opcode (reserved instruction). See sim_monitor and its
# callers in sim/mips/interp.c.
- .word 0x00000005 | ((8 << 1) << 6)
+ .word 0x00000039 | ((8 << 1) << 6)
.end _dowrite
.endm # setup