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| author | Jim Wilson <jim.wilson@linaro.org> | 2016-12-21 12:33:12 -0800 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2016-12-21 12:33:12 -0800 |
| commit | 87903eafb083abbf330c22fbf941fcbad700c098 (patch) | |
| tree | 832a5f42fb2e2488edc7a47f8f9e23225e39c1a7 /sim/testsuite | |
| parent | f0d19df99dfe1c63842206d15ae41dfd33d25bf0 (diff) | |
| download | gdb-87903eafb083abbf330c22fbf941fcbad700c098.zip gdb-87903eafb083abbf330c22fbf941fcbad700c098.tar.gz gdb-87903eafb083abbf330c22fbf941fcbad700c098.tar.bz2 | |
Fix bugs with float compare and Inf operands.
sim/aarch64/
* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
Add comment to document NaN issue.
(set_flags_for_double_compare): Likewise.
sim/testsuite/sim/aarch64/
* fcmp.s: New.
Diffstat (limited to 'sim/testsuite')
| -rw-r--r-- | sim/testsuite/sim/aarch64/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/testsuite/sim/aarch64/fcmp.s | 146 |
2 files changed, 150 insertions, 0 deletions
diff --git a/sim/testsuite/sim/aarch64/ChangeLog b/sim/testsuite/sim/aarch64/ChangeLog index ff047e3..a130a97 100644 --- a/sim/testsuite/sim/aarch64/ChangeLog +++ b/sim/testsuite/sim/aarch64/ChangeLog @@ -1,3 +1,7 @@ +2016-12-21 Jim Wilson <jim.wilson@linaro.org> + + * fcmp.s: New. + 2016-12-13 Jim Wilson <jim.wilson@linaro.org> * testutils.inc (pass): Move .Lpass to start. diff --git a/sim/testsuite/sim/aarch64/fcmp.s b/sim/testsuite/sim/aarch64/fcmp.s new file mode 100644 index 0000000..fd826c4 --- /dev/null +++ b/sim/testsuite/sim/aarch64/fcmp.s @@ -0,0 +1,146 @@ +# mach: aarch64 + +# Check the FP compare instructions: fcmps, fcmpzs, fcmpes, fcmpzes, fcmpd, +# fcmpzd, fcmped, fcmpzed. +# For 1 operand compares, check 0, 1, -1, +Inf, -Inf. +# For 2 operand compares, check 1/1, 1/-2, -1/2, +Inf/+Inf, +Inf/-Inf. +# FIXME: Check for qNaN and sNaN when exception raising support added. + +.include "testutils.inc" + + start + fmov s0, wzr + fcmp s0, #0.0 + bne .Lfailure + fcmpe s0, #0.0 + bne .Lfailure + fmov d0, xzr + fcmp d0, #0.0 + bne .Lfailure + fcmpe d0, #0.0 + bne .Lfailure + + fmov s0, #1.0 + fcmp s0, #0.0 + blo .Lfailure + fcmpe s0, #0.0 + blo .Lfailure + fmov d0, #1.0 + fcmp d0, #0.0 + blo .Lfailure + fcmpe d0, #0.0 + blo .Lfailure + + fmov s0, #-1.0 + fcmp s0, #0.0 + bpl .Lfailure + fcmpe s0, #0.0 + bpl .Lfailure + fmov d0, #-1.0 + fcmp d0, #0.0 + bpl .Lfailure + fcmpe d0, #0.0 + bpl .Lfailure + + fmov s0, #1.0 + fmov s1, wzr + fdiv s0, s0, s1 + fcmp s0, #0.0 + blo .Lfailure + fcmpe s0, #0.0 + blo .Lfailure + fmov d0, #1.0 + fmov d1, xzr + fdiv d0, d0, d1 + fcmp d0, #0.0 + blo .Lfailure + fcmpe d0, #0.0 + blo .Lfailure + + fmov s0, #-1.0 + fmov s1, wzr + fdiv s0, s0, s1 + fcmp s0, #0.0 + bpl .Lfailure + fcmpe s0, #0.0 + bpl .Lfailure + fmov d0, #-1.0 + fmov d1, xzr + fdiv d0, d0, d1 + fcmp d0, #0.0 + bpl .Lfailure + fcmpe d0, #0.0 + bpl .Lfailure + + fmov s0, #1.0 + fmov s1, #1.0 + fcmp s0, s1 + bne .Lfailure + fcmpe s0, s1 + bne .Lfailure + fmov d0, #1.0 + fmov d1, #1.0 + fcmp d0, d1 + bne .Lfailure + fcmpe d0, d1 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, #-2.0 + fcmp s0, s1 + blo .Lfailure + fcmpe s0, s1 + blo .Lfailure + fmov d0, #1.0 + fmov d1, #-2.0 + fcmp d0, d1 + blo .Lfailure + fcmpe d0, d1 + blo .Lfailure + + fmov s0, #-1.0 + fmov s1, #2.0 + fcmp s0, s1 + bpl .Lfailure + fcmpe s0, s1 + bpl .Lfailure + fmov d0, #-1.0 + fmov d1, #2.0 + fcmp d0, d1 + bpl .Lfailure + fcmpe d0, d1 + bpl .Lfailure + + fmov s0, #1.0 + fmov s1, wzr + fdiv s0, s0, s1 + fcmp s0, s0 + bne .Lfailure + fcmpe s0, s0 + bne .Lfailure + fmov s1, #-1.0 + fmov s2, wzr + fdiv s1, s1, s2 + fcmp s0, s1 + blo .Lfailure + fcmpe s0, s1 + blo .Lfailure + + fmov d0, #1.0 + fmov d1, xzr + fdiv d0, d0, d1 + fcmp d0, d0 + bne .Lfailure + fcmpe d0, d0 + bne .Lfailure + fmov d1, #-1.0 + fmov d2, xzr + fdiv d1, d1, d2 + fcmp d0, d1 + blo .Lfailure + fcmpe d0, d1 + blo .Lfailure + + pass +.Lfailure: + fail |