2003-10-10 Dave Brolley <brolley@redhat.com>

        * sim/frv/testutils.inc (or_gr_immed): New macro.
        * sim/frv/fp_exception-fr550.cgs: Write insns using
        unaligned registers into the program in order to
        cause the required exceptions.
        * sim/frv/fp_exception.cgs: Ditto.
        * sim/frv/regalign.cgs: Ditto.

5 files changed, 99 insertions, 10 deletions

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 83f87b7..cbd36e3 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2003-10-10  Dave Brolley  <brolley@redhat.com>
+
+	* sim/frv/testutils.inc (or_gr_immed): New macro.
+	* sim/frv/fp_exception-fr550.cgs: Write insns using
+	unaligned registers into the program in order to
+	cause the required exceptions.
+	* sim/frv/fp_exception.cgs: Ditto.
+	* sim/frv/regalign.cgs: Ditto.
+
 2003-10-06  Dave Brolley  <brolley@redhat.com>
 
 	* sim/frv/fr550: New subdirectory.
diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
index bd1ee44..0bb98d8 100644
--- a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
+++ b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
@@ -16,6 +16,24 @@ align:
 	set_gr_addr	pack,gr10
 	flush_data_cache gr10
 
+	; Make the the source register number odd at badst. We can't simply
+	; code an odd register number because the assembler will catch the
+	; error.
+	set_gr_mem	badst,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,badst
+	set_gr_addr	badst,gr10
+	flush_data_cache gr10
+
+	; Make the the dest register number odd at badld. We can't simply
+	; code an odd register number because the assembler will catch the
+	; error.
+	set_gr_mem	badld,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,badld
+	set_gr_addr	badld,gr10
+	flush_data_cache gr10
+
 	and_spr_immed	-4081,tbr		; clear tbr.tt
 	set_gr_spr	tbr,gr17
 	inc_gr_immed	0x070,gr17		; address of exception handler
@@ -32,13 +50,13 @@ align:
 
 	set_spr_addr	ok3,lr
 	set_gr_immed	4,gr20		; PC increment
-badst1:	stdfi		fr1,@(sp,0)	; misaligned reg -- slot I0
+badst:	stdfi		fr0,@(sp,0)	; misaligned reg -- slot I0
 	test_gr_immed	1,gr15
 
 	set_spr_addr	ok4,lr
 	set_gr_immed	8,gr20		; PC increment
 	nop.p
-badst2:	lddfi		@(sp,0),fr9	; misaligned reg -- slot I1
+badld:	lddfi		@(sp,0),fr8	; misaligned reg -- slot I1
 	test_gr_immed	2,gr15
 
 	set_spr_addr	ok5,lr
diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs
index 710b5ba..ad5f7e4 100644
--- a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs
+++ b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs
@@ -16,6 +16,24 @@ align:
 	set_gr_addr	pack,gr10
 	flush_data_cache gr10
 
+	; Make the the source register number odd at badst. We can't simply
+	; code an odd register number because the assembler will catch the
+	; error.
+	set_gr_mem	badst,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,badst
+	set_gr_addr	badst,gr10
+	flush_data_cache gr10
+
+	; Make the the dest register number odd at ld. We can't simply
+	; code an odd register number because the assembler will catch the
+	; error.
+	set_gr_mem	badld,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,badld
+	set_gr_addr	badld,gr10
+	flush_data_cache gr10
+
 	and_spr_immed	-4081,tbr		; clear tbr.tt
 	set_gr_spr	tbr,gr17
 	inc_gr_immed	0x070,gr17		; address of exception handler
@@ -31,12 +49,12 @@ align:
 	set_gr_immed	0,gr15
 
 	set_spr_addr	ok3,lr
-	stdfi		fr1,@(sp,0)	; misaligned reg -- slot I0
+badst:	stdfi		fr0,@(sp,0)	; misaligned reg -- slot I0
 	test_gr_immed	1,gr15
 
 	set_spr_addr	ok4,lr
 	nop.p
-	lddfi		@(sp,0),fr9	; misaligned reg -- slot I1
+badld:	lddfi		@(sp,0),fr8	; misaligned reg -- slot I1
 	test_gr_immed	2,gr15
 
 	set_spr_addr	ok5,lr
diff --git a/sim/testsuite/sim/frv/interrupts/regalign.cgs b/sim/testsuite/sim/frv/interrupts/regalign.cgs
index e113753..afa09b5 100644
--- a/sim/testsuite/sim/frv/interrupts/regalign.cgs
+++ b/sim/testsuite/sim/frv/interrupts/regalign.cgs
@@ -16,24 +16,58 @@ align:
 	set_spr_addr	ok1,lr
 	set_psr_et	1
 
+	; Make the the register number odd at bad[1-4], bad9 and bada.
+	; We can't simply code an odd register number because the assembler
+	; will catch the error.
+	set_gr_mem	bad1,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,bad1
+	set_gr_addr	bad1,gr10
+	flush_data_cache gr10
+	set_gr_mem	bad2,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,bad2
+	set_gr_addr	bad2,gr10
+	flush_data_cache gr10
+	set_gr_mem	bad3,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,bad3
+	set_gr_addr	bad3,gr10
+	flush_data_cache gr10
+	set_gr_mem	bad4,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,bad4
+	set_gr_addr	bad4,gr10
+	flush_data_cache gr10
+	set_gr_mem	bad9,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,bad9
+	set_gr_addr	bad9,gr10
+	flush_data_cache gr10
+	set_gr_mem	bada,gr10
+	or_gr_immed	0x02000000,gr10
+	set_mem_gr	gr10,bada
+	set_gr_addr	bada,gr10
+	flush_data_cache gr10
+
 	set_gr_immed	4,gr20		; PC increment
 	set_gr_immed	0,gr15
 	inc_gr_immed	-12,sp		; for memory alignment
 
 	set_gr_addr	bad1,gr17
-bad1:	stdi	gr1,@(sp,0)		; misaligned reg
+bad1:	stdi	gr0,@(sp,0)		; misaligned reg
 	test_gr_immed	1,gr15
 
 	set_gr_addr	bad2,gr17
-bad2:	lddi	@(sp,0),gr9		; misaligned reg
+bad2:	lddi	@(sp,0),gr8		; misaligned reg
 	test_gr_immed	2,gr15
 
 	set_gr_addr	bad3,gr17
-bad3:	stdc	cpr1,@(sp,gr0)		; misaligned reg
+bad3:	stdc	cpr0,@(sp,gr0)		; misaligned reg
 	test_gr_immed	3,gr15
 
 	set_gr_addr	bad4,gr17
-bad4:	lddc	@(sp,gr0),cpr9		; misaligned reg
+bad4:	lddc	@(sp,gr0),cpr8		; misaligned reg
 	test_gr_immed	4,gr15
 
 	set_gr_addr	bad5,gr17
@@ -54,11 +88,11 @@ bad8:	ldqc	@(sp,gr0),cpr10		; misaligned reg
 
 	set_gr_immed	0,gr20		; PC increment
 	set_gr_addr	bad9,gr17
-bad9:	stdfi	fr1,@(sp,0)		; misaligned reg
+bad9:	stdfi	fr0,@(sp,0)		; misaligned reg
 	test_gr_immed	9,gr15
 
 	set_gr_addr	bada,gr17
-bada:	lddfi	@(sp,0),fr9		; misaligned reg
+bada:	lddfi	@(sp,0),fr8		; misaligned reg
 	test_gr_immed	10,gr15
 
 	set_gr_addr	badb,gr17
diff --git a/sim/testsuite/sim/frv/testutils.inc b/sim/testsuite/sim/frv/testutils.inc
index e9bfd86..8261b4fa 100644
--- a/sim/testsuite/sim/frv/testutils.inc
+++ b/sim/testsuite/sim/frv/testutils.inc
@@ -97,6 +97,16 @@ nofsr0:
 	.endif
 	.endm
 
+; OR GR with immediate value
+	.macro or_gr_immed val reg
+	.if (\val >= -2048) && (\val <= 2047)
+	ori \reg,\val,\reg
+	.else
+	set_gr_immed \val,gr28
+	or \reg,gr28,\reg
+	.endif
+	.endm
+
 ; Set FR with another FR
 	.macro set_fr_fr src targ
 	fmovs	\src,\targ