sim: bfin: add tests for recent dsp fixes

Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
author: Mike Frysinger <vapier@gentoo.org> 2011-06-18 20:27:26 +0000
committer: Mike Frysinger <vapier@gentoo.org> 2011-06-18 20:27:26 +0000
commit: 4bd2c0c31ccea3032031648e7497bb7d1c04cc39 (patch)
tree: 6838d746b4775522de45e3065bcf81f9fa8d2db0 /sim/testsuite
parent: a0a71a7f8b85f3d25403d140b7fb14b54b3e7f4a (diff)
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14 files changed, 2502 insertions, 0 deletions
diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog
index da2b202..ec487df 100644
--- a/sim/testsuite/sim/bfin/ChangeLog
+++ b/sim/testsuite/sim/bfin/ChangeLog
@@ -1,3 +1,10 @@
+2011-06-18  Robin Getz  <robin.getz@analog.com>
+
+	* random_0019.S, random_0020.S, random_0021.S, random_0022.S,
+	random_0023.S, random_0024.S, random_0026.S, random_0027.S,
+	random_0028.S, random_0029.S, random_0030.S, random_0032.S,
+	random_0035.S: New tests for dsp insns.
+
 2011-06-04  Mike Frysinger  <vapier@gentoo.org>
 
 	* .gitignore, 10272_small.s, 10436.s, 10622.s, 10742.s, 10799.s,
diff --git a/sim/testsuite/sim/bfin/random_0019.S b/sim/testsuite/sim/bfin/random_0019.S
new file mode 100644
index 0000000..2da09c4
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0019.S
@@ -0,0 +1,216 @@
+# Test a few (W32) corner cases
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV0S | _CC | _AC0_COPY | _AN | _AZ);
+	dmm32 A1.w, 0x70da33ff;
+	dmm32 A1.x, 0x0000000f;
+	imm32 R0, 0x5e29f819;
+	imm32 R1, 0x3f59520b;
+	A1 += R0.L * R1.L (M, W32);
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV1 | _AV0S | _CC | _AC0_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x18300c10 | _VS | _AV1S | _AN);
+	dmm32 A0.w, 0x1096b1c1;
+	dmm32 A0.x, 0xfffffff1;
+	imm32 R6, 0x3a0178ee;
+	imm32 R7, 0x17c95e45;
+	A0 -= R6.L * R7.L (W32);
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x18300c10 | _VS | _AV1S | _AV0S | _AV0 | _AN);
+
+	dmm32 ASTAT, (0x68508800 | _VS | _AV1S | _AV0S | _CC | _AZ);
+	dmm32 A0.w, 0x30c8f917;
+	dmm32 A0.x, 0xffffffc8;
+	imm32 R3, 0x7ad1091c;
+	imm32 R4, 0x80002874;
+	A0 -= R3.L * R4.L (W32);
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x68508800 | _VS | _AV1S | _AV0S | _AV0 | _CC | _AZ);
+
+	dmm32 ASTAT, (0x58708e90 | _VS | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY);
+	dmm32 A0.w, 0x13de4c3d;
+	dmm32 A0.x, 0xffffffa5;
+	imm32 R0, 0xf70f956f;
+	imm32 R2, 0xf837e08c;
+	A0 -= R0.L * R2.H (W32);
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x58708e90 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY);
+
+	dmm32 ASTAT, (0x70800280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY);
+	dmm32 A0.w, 0x80140410;
+	dmm32 A0.x, 0x00000000;
+	imm32 R1, 0x028b09a4;
+	imm32 R4, 0x00007ffc;
+	A0 += R4.L * R1.H (W32);
+	checkreg A0.w, 0x7fffffff;
+	checkreg A0.x, 0x00000000;
+	checkreg ASTAT, (0x70800280 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY);
+
+	dmm32 ASTAT, (0x0060c610 | _VS | _AC1 | _AC0 | _AC0_COPY | _AN | _AZ);
+	dmm32 A1.w, 0x1794b937;
+	dmm32 A1.x, 0xfffffff5;
+	imm32 R6, 0x008e1c0d;
+	A1 -= R6.L * R6.L (W32);
+	checkreg A1.w, 0x80000000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x0060c610 | _VS | _AV1S | _AV1 | _AC1 | _AC0 | _AC0_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x2c600410 | _VS | _AV0S | _AC1 | _CC | _AN);
+	dmm32 A1.w, 0x2d03ef79;
+	dmm32 A1.x, 0x00000079;
+	imm32 R5, 0x15d1b500;
+	imm32 R6, 0xf7962b39;
+	A1 += R6.L * R5.H (W32);
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x2c600410 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _CC | _AN);
+
+	dmm32 ASTAT, (0x5cf04e10 | _VS | _AV0S | _AC1 | _CC | _AC0_COPY);
+	dmm32 A0.w, 0x4d50b3f0;
+	dmm32 A0.x, 0xfffffffc;
+	imm32 R4, 0x6671002a;
+	imm32 R7, 0x00288000;
+	A0 += R4.L * R7.L (W32);
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x5cf04e10 | _VS | _AV0S | _AV0 | _AC1 | _CC | _AC0_COPY);
+
+
+	dmm32 ASTAT, (0x28908000 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AN);
+	dmm32 A1.w, 0xc94e99f1;
+	dmm32 A1.x, 0x00000021;
+	imm32 R4, 0x7fff52b7;
+	imm32 R7, 0x3ebb26c6;
+	A1 += R7.L * R4.L (M, W32);
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x28908000 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x34708a00 | _VS | _AV0S | _AQ | _CC | _AC0_COPY);
+	dmm32 A1.w, 0xf61f316d;
+	dmm32 A1.x, 0x00000061;
+	imm32 R1, 0x86f0ffff;
+	imm32 R3, 0x791048c5;
+	A1 += R1.L * R3.L (M, W32);
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x34708a00 | _VS | _AV1S | _AV1 | _AV0S | _AQ | _CC | _AC0_COPY);
+
+	dmm32 ASTAT, (0x5020c280 | _VS | _V | _AC1 | _AC0 | _V_COPY);
+	dmm32 A1.w, 0x8700591f;
+	dmm32 A1.x, 0x00000007;
+	imm32 R2, 0x145b00b1;
+	imm32 R3, 0x7fffffff;
+	A1 -= R3.L * R2.H (M, W32);
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x5020c280 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _V_COPY);
+
+	dmm32 ASTAT, (0x00000290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
+	dmm32 A0.w, 0xfe84e1ec;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R1, 0x07e73e7b;
+	imm32 R3, 0x00033e7b;
+	A0 -= R3.L * R1.H (W32);
+	checkreg A0.w, 0xfaa965f2;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x00000290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x78204a80 | _VS | _AV1S | _CC | _AN);
+	dmm32 A0.w, 0xca398210;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R3, 0xffff0000;
+	imm32 R7, 0x00000000;
+	A0 += R7.L * R3.L (W32);
+	checkreg ASTAT, (0x78204a80 | _VS | _AV1S | _CC | _AN);
+
+	dmm32 ASTAT, (0x04208890 | _VS | _AC1 | _AC0_COPY);
+	dmm32 A0.w, 0x224cbaee;
+	dmm32 A0.x, 0x00000000;
+	imm32 R3, 0x3db86584;
+	imm32 R6, 0xdb505ed8;
+	A0 -= R6.L * R3.H (W32);
+	checkreg A0.w, 0xf491746e;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x04208890 | _VS | _AC1 | _AC0_COPY);
+
+	dmm32 ASTAT, (0x3c908600 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
+	dmm32 A0.w, 0x03f7c0ec;
+	dmm32 A0.x, 0x00000000;
+	imm32 R1, 0x1c25c7b4;
+	imm32 R5, 0x3f7da612;
+	A0 -= R5.L * R1.L (W32);
+	checkreg A0.w, 0xdc6a3b9c;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x3c908600 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
+
+	dmm32 ASTAT, (0x7cb08680 | _VS | _AQ | _CC | _AN);
+	dmm32 A0.w, 0xdc7c243c;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R0, 0xe2ccef4c;
+	imm32 R5, 0x7fff8000;
+	A0 += R5.L * R0.L (W32);
+	checkreg A0.w, 0xed30243c;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x7cb08680 | _VS | _AQ | _CC | _AN);
+
+	dmm32 ASTAT, (0x78f00080 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AN);
+	dmm32 A0.w, 0x39180f38;
+	dmm32 A0.x, 0x00000000;
+	imm32 R4, 0x01308ac1;
+	imm32 R6, 0x7ffff8fd;
+	A0 = R6.L * R4.H (W32);
+	checkreg A0.w, 0xffef58e0;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x78f00080 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x7050c090 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x010909b0;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x80000000;
+	imm32 R6, 0x6ad06150;
+	A1 = R6.L * R0.H (W32);
+	checkreg A1.w, 0x9eb00000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x7050c090 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x68c04c10 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AN);
+	dmm32 A0.w, 0x43687862;
+	dmm32 A0.x, 0x00000000;
+	imm32 R2, 0xff278000;
+	imm32 R4, 0x0000436a;
+	A0 += R2.L * R4.L (W32);
+	checkreg A0.w, 0xfffe7862;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x68c04c10 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x74a00200 | _AV1 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY | _AN | _AZ);
+	dmm32 A1.w, 0x64c15e6b;
+	dmm32 A1.x, 0xffffff87;
+	imm32 R4, 0x30b3e20d;
+	imm32 R7, 0x4a562069;
+	A1 = R4.L * R7.H (M, W32);
+	checkreg A1.w, 0xf74db25e;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x74a00200 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x70f08410 | _AV0 | _AC1 | _AC0_COPY | _AN | _AZ);
+	dmm32 A0.w, 0x5f011b0d;
+	dmm32 A0.x, 0xffffff86;
+	imm32 R3, 0x21f93a90;
+	imm32 R4, 0x1c82d429;
+	A0 = R3.H * R4.L (W32);
+	checkreg A0.w, 0xf45d49c2;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x70f08410 | _AC1 | _AC0_COPY | _AN | _AZ);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0020.S b/sim/testsuite/sim/bfin/random_0020.S
new file mode 100644
index 0000000..d140fb1
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0020.S
@@ -0,0 +1,434 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
+	dmm32 A1.w, 0xfcdbede4;
+	dmm32 A1.x, 0xffffffff;
+		imm32 R5, 0x14c5c1c7;
+		imm32 R7, 0x006a5040;
+	R5 = (A1 += R7.L * R7.H) (M, IU);
+		checkreg R5, 0xfcfd2864;
+		checkreg A1.w, 0xfcfd2864;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
+
+	dmm32 ASTAT, (0x6c508a90 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0x0bcd165c;
+	dmm32 A1.x, 0x00000000;
+		imm32 R0, 0x439a7ef1;
+		imm32 R3, 0x47670015;
+		imm32 R6, 0x00008000;
+	R3 = (A1 += R6.L * R0.L) (M, IU);
+		checkreg R3, 0xcc54965c;
+		checkreg A1.w, 0xcc54965c;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x6c508a90 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY);
+
+	dmm32 ASTAT, (0x38900480 | _VS | _AV0S | _AN);
+	dmm32 A1.w, 0x00000000;
+	dmm32 A1.x, 0x00000000;
+		imm32 R1, 0x8000ffff;
+		imm32 R3, 0x0000ffff;
+		imm32 R6, 0xcb2cf810;
+	R3 = (A1 += R6.L * R1.L) (M, IU);
+		checkreg R3, 0xf81007f0;
+		checkreg A1.w, 0xf81007f0;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x38900480 | _VS | _AV0S | _AN);
+
+	dmm32 ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN);
+	dmm32 A1.w, 0x36491cf0;
+	dmm32 A1.x, 0x00000000;
+		imm32 R1, 0x10771108;
+		imm32 R2, 0x7fb14fe2;
+		imm32 R7, 0x3649ffff;
+	R1 = (A1 = R7.L * R2.H) (M, IU);
+		checkreg R1, 0xffff804f;
+		checkreg A1.w, 0xffff804f;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN);
+
+	dmm32 ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ);
+	dmm32 A1.w, 0xd831c3b7;
+	dmm32 A1.x, 0xffffffff;
+		imm32 R3, 0x3a98144b;
+		imm32 R7, 0xd831c3b7;
+	R7 = (A1 -= R3.L * R3.H) (M, IU);
+		checkreg R7, 0xd38cb92f;
+		checkreg A1.w, 0xd38cb92f;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ);
+
+	dmm32 ASTAT, (0x3c50c810 | _VS | _AV1S | _AN | _AZ);
+	dmm32 A0.w, 0x13cd1c6c;
+	dmm32 A0.x, 0x00000000;
+		imm32 R2, 0x4000e935;
+		imm32 R3, 0xe0b313cd;
+	R3.L = (A0 += R3.H * R2.L) (IU);
+		checkreg R3, 0xe0b3ffff;
+		checkreg A0.w, 0xe07e8c7b;
+		checkreg A0.x, 0x00000000;
+		checkreg ASTAT, (0x3c50c810 | _VS | _V | _AV1S | _V_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ);
+	dmm32 A0.w, 0x057e5874;
+	dmm32 A0.x, 0x00000000;
+		imm32 R0, 0x1c0af520;
+		imm32 R6, 0x7caea317;
+		imm32 R7, 0x107e8ce4;
+	R6.L = (A0 += R7.L * R0.L) (IU);
+		checkreg R6, 0x7caeffff;
+		checkreg A0.w, 0x8c6628f4;
+		checkreg A0.x, 0x00000000;
+		checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY);
+
+	dmm32 ASTAT, (0x6cf04090 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
+	dmm32 A0.w, 0xdc7d7b8c;
+	dmm32 A0.x, 0x00000000;
+		imm32 R0, 0x788e00d2;
+		imm32 R6, 0x03666070;
+	R0.L = (A0 -= R6.H * R6.H) (IU);
+		checkreg R0, 0x788effff;
+		checkreg A0.w, 0xdc71eee8;
+		checkreg A0.x, 0x00000000;
+		checkreg ASTAT, (0x6cf04090 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AZ);
+
+	dmm32 ASTAT, (0x4cc04c80 | _VS | _CC);
+	dmm32 A1.w, 0x41620ea7;
+	dmm32 A1.x, 0x00000057;
+		imm32 R1, 0xf611262c;
+		imm32 R3, 0x7fff7fff;
+		imm32 R4, 0x247ee19c;
+	R1 = (A1 += R4.L * R3.L) (IU);
+		checkreg R1, 0xffffffff;
+		checkreg A1.w, 0xb22f2d0b;
+		checkreg A1.x, 0x00000057;
+		checkreg ASTAT, (0x4cc04c80 | _VS | _V | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x28e04610 | _VS | _AV0S | _AC1 | _AC0 | _AN);
+	dmm32 A0.w, 0xe1753d16;
+	dmm32 A0.x, 0xffffffff;
+		imm32 R0, 0x7fffffff;
+		imm32 R5, 0x2792ffff;
+		imm32 R7, 0xffffd6fa;
+	R7.L = (A0 = R0.L * R5.L) (IU);
+		checkreg R7, 0xffffffff;
+		checkreg A0.w, 0xfffe0001;
+		checkreg A0.x, 0x00000000;
+		checkreg ASTAT, (0x28e04610 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ);
+	dmm32 A0.w, 0x057e5874;
+	dmm32 A0.x, 0x00000000;
+		imm32 R0, 0x1c0af520;
+		imm32 R6, 0x7caea317;
+		imm32 R7, 0x107e8ce4;
+	R6.L = (A0 += R7.L * R0.L) (IU);
+		checkreg R6, 0x7caeffff;
+		checkreg A0.w, 0x8c6628f4;
+		checkreg A0.x, 0x00000000;
+		checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY);
+
+	dmm32 ASTAT, (0x00304000 | _VS | _AV1S | _AQ | _AZ);
+	dmm32 A0.w, 0x615bac86;
+	dmm32 A0.x, 0x00000000;
+		imm32 R2, 0x6d2cbec6;
+		imm32 R3, 0xe09db667;
+	R3.L = (A0 += R3.H * R2.H) (IU);
+		checkreg R3, 0xe09dffff;
+		checkreg A0.w, 0xc1252082;
+		checkreg A0.x, 0x00000000;
+		checkreg ASTAT, (0x00304000 | _VS | _V | _AV1S | _AQ | _V_COPY | _AZ);
+
+	dmm32 ASTAT, (0x5cc00080 | _VS | _AV1S | _AC0 | _CC);
+	dmm32 A1.w, 0x70d9985a;
+	dmm32 A1.x, 0xffffffd6;
+		imm32 R1, 0x8000fdeb;
+		imm32 R2, 0x20e07e89;
+	R1.H = (A1 += R2.L * R1.L) (M, IU);
+		checkreg A1.w, 0xee5b251d;
+		checkreg A1.x, 0xffffffd6;
+		checkreg ASTAT, (0x5cc00080 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x60e0ce80 | _VS | _AC0 | _AQ | _CC);
+	dmm32 A1.w, 0x67798cf6;
+	dmm32 A1.x, 0x00000044;
+	imm32 R0, 0x00000000;
+	imm32 R1, 0x00008e16;
+	imm32 R7, 0x00000000;
+	R7 = (A1 -= R0.L * R1.L) (M, IU);
+	checkreg R7, 0x7fffffff;
+	checkreg A1.w, 0x67798cf6;
+	checkreg A1.x, 0x00000044;
+	checkreg ASTAT, (0x60e0ce80 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0x6f47fe74;
+	dmm32 A1.x, 0x00000022;
+		imm32 R5, 0x3482aa64;
+		imm32 R6, 0x48320cd9;
+	R5.H = (A1 -= R6.L * R5.L) (M, IU);
+		checkreg R5, 0x7fffaa64;
+		checkreg A1.w, 0x66badfb0;
+		checkreg A1.x, 0x00000022;
+		checkreg ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0x43fdb94f;
+	dmm32 A1.x, 0xffffff97;
+		imm32 R1, 0x80000000;
+		imm32 R7, 0x0f9b234b;
+	R1.H = (A1 += R7.L * R1.H) (M, IU);
+		checkreg A1.w, 0x55a3394f;
+		checkreg A1.x, 0xffffff97;
+		checkreg ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x60f0c280 | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
+	dmm32 A1.w, 0x33205f9e;
+	dmm32 A1.x, 0xfffffffc;
+		imm32 R3, 0x39e0545d;
+		imm32 R6, 0x0e133731;
+	R3 = (A1 -= R3.L * R6.H) (M, IU);
+		checkreg R3, 0x80000000;
+		checkreg A1.w, 0x2e7d06b7;
+		checkreg A1.x, 0xfffffffc;
+		checkreg ASTAT, (0x60f0c280 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x6c300490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x2a477a36;
+	dmm32 A1.x, 0xfffffff8;
+		imm32 R0, 0xff020000;
+		imm32 R5, 0x00000000;
+		imm32 R7, 0xffff8000;
+	R5.H = (A1 -= R0.L * R7.H) (M, IU);
+		checkreg R5, 0x80000000;
+		checkreg ASTAT, (0x6c300490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x1400c210 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN);
+	dmm32 A1.w, 0x68033dca;
+	dmm32 A1.x, 0xffffffff;
+		imm32 R1, 0x00000000;
+		imm32 R3, 0x00a36a42;
+		imm32 R7, 0x3afd7fff;
+	R3.H = (A1 -= R1.L * R7.H) (M, IU);
+		checkreg R3, 0x80006a42;
+		checkreg ASTAT, (0x1400c210 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x00104810 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xeb4e9a1d;
+	dmm32 A1.x, 0xffffff8c;
+		imm32 R1, 0xffffec05;
+		imm32 R5, 0x80000000;
+		imm32 R6, 0x5ffa604a;
+	R1.H = (A1 += R6.L * R5.H) (M, IU);
+		checkreg R1, 0x8000ec05;
+		checkreg A1.w, 0x1b739a1d;
+		checkreg A1.x, 0xffffff8d;
+		checkreg ASTAT, (0x00104810 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x48600280 | _VS | _AV1S | _AV0 | _AC1 | _CC | _AC0_COPY);
+	dmm32 A1.w, 0x54463e5f;
+	dmm32 A1.x, 0xffffff94;
+		imm32 R1, 0x2e0d6820;
+		imm32 R4, 0x37855c3d;
+		imm32 R6, 0x7b3ca7a0;
+	R6.H = (A1 += R4.L * R1.L) (M, IU);
+		checkreg R6, 0x8000a7a0;
+		checkreg A1.w, 0x79ca8dff;
+		checkreg A1.x, 0xffffff94;
+		checkreg ASTAT, (0x48600280 | _VS | _V | _AV1S | _AV0 | _AC1 | _CC | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x3c008480 | _VS | _AV1S | _AC1 | _AC0 | _CC);
+	dmm32 A0.w, 0xcdff712a;
+	dmm32 A0.x, 0xffffffff;
+		imm32 R0, 0x2f3dfc31;
+		imm32 R2, 0x1b1a4b4c;
+		imm32 R6, 0x7cbed409;
+	R2 = (A0 += R6.H * R0.L) (IU);
+		checkreg R2, 0xffffffff;
+		checkreg A0.w, 0xffffffff;
+		checkreg A0.x, 0xffffffff;
+		checkreg ASTAT, (0x3c008480 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x4ce0ce80 | _VS | _AC1 | _AC0 | _CC);
+	dmm32 A0.w, 0xfefe27a4;
+	dmm32 A0.x, 0xffffffff;
+		imm32 R0, 0x08270055;
+		imm32 R1, 0x0000ffc2;
+		imm32 R6, 0x5ca7213b;
+	R6.L = (A0 += R1.L * R0.H) (IU);
+		checkreg R6, 0x5ca7ffff;
+		checkreg A0.w, 0xffffffff;
+		checkreg A0.x, 0xffffffff;
+		checkreg ASTAT, (0x4ce0ce80 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x7020ca10 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY);
+	dmm32 A0.w, 0xec60b144;
+	dmm32 A0.x, 0xffffffff;
+		imm32 R0, 0x147e9190;
+		imm32 R1, 0x2b813e9e;
+		imm32 R4, 0xab65ffff;
+	R0 = (A0 += R1.L * R4.H) (IU);
+		checkreg R0, 0xffffffff;
+		checkreg A0.w, 0xffffffff;
+		checkreg A0.x, 0xffffffff;
+		checkreg ASTAT, (0x7020ca10 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x28e08210 | _VS | _AQ | _AN);
+	dmm32 A0.w, 0xe650ec98;
+	dmm32 A0.x, 0xffffffff;
+		imm32 R1, 0xcca1b6ef;
+		imm32 R2, 0xd762b783;
+		imm32 R3, 0xef34e465;
+	R2 = (A0 += R3.L * R1.H) (IU);
+		checkreg R2, 0xffffffff;
+		checkreg A0.w, 0xffffffff;
+		checkreg A0.x, 0xffffffff;
+		checkreg ASTAT, (0x28e08210 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x58904e00 | _VS | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
+	dmm32 A0.w, 0xb84b0e88;
+	dmm32 A0.x, 0xffffffff;
+		imm32 R0, 0x8367ffff;
+		imm32 R1, 0xb6a1af0a;
+	R1.L = (A0 += R0.H * R1.H) (IU);
+		checkreg R1, 0xb6a1ffff;
+		checkreg A0.w, 0xffffffff;
+		checkreg A0.x, 0xffffffff;
+		checkreg ASTAT, (0x58904e00 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x30900810 | _VS | _AV1S | _AC1 | _AQ | _CC);
+	dmm32 A1.w, 0xd0762eff;
+	dmm32 A1.x, 0xffffffff;
+		imm32 R0, 0x00000000;
+		imm32 R1, 0x1d9b7fff;
+		imm32 R3, 0xf32bf32b;
+	R0.H = (A1 += R1.L * R3.L) (M, IU);
+		checkreg R0, 0x7fff0000;
+		checkreg A1.w, 0x4a0abbd4;
+		checkreg A1.x, 0x00000000;
+		checkreg ASTAT, (0x30900810 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
+	dmm32 A1.w, 0xf1008000;
+	dmm32 A1.x, 0xffffffff;
+		imm32 R3, 0x0bb78001;
+		imm32 R5, 0x0be78000;
+		imm32 R7, 0x17cd9a40;
+	R3.H = (A1 += R7.L * R5.L) (M, IU);
+		checkreg R3, 0x80008001;
+		checkreg A1.w, 0xbe208000;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x40900490 | _VS | _AV1S);
+	dmm32 A1.w, 0xa9d97d12;
+	dmm32 A1.x, 0xffffffff;
+		imm32 R0, 0x4e01ffff;
+		imm32 R3, 0x12abdd35;
+		imm32 R7, 0xa9d966d6;
+	R7.H = (A1 += R0.L * R3.L) (M, IU);
+		checkreg R7, 0x800066d6;
+		checkreg A1.w, 0xa9d89fdd;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x40900490 | _VS | _V | _AV1S | _V_COPY);
+
+	dmm32 ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
+	dmm32 A1.w, 0xe552d880;
+	dmm32 A1.x, 0xffffffff;
+		imm32 R3, 0xfe6bf901;
+		imm32 R5, 0xfae40000;
+		imm32 R6, 0x3917f106;
+	R5.H = (A1 += R6.L * R3.H) (M, IU);
+		checkreg R5, 0x80000000;
+		checkreg A1.w, 0xd6708a02;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x2050c490 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xfcd2b056;
+	dmm32 A1.x, 0xffffffff;
+		imm32 R2, 0xff36c118;
+		imm32 R4, 0xfffe0001;
+		imm32 R7, 0x7fff00f4;
+	R7.H = (A1 += R2.L * R4.H) (M, IU);
+		checkreg R7, 0x800000f4;
+		checkreg A1.w, 0xbdeb2e26;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x2050c490 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
+	dmm32 A1.w, 0x391f1bbc;
+	dmm32 A1.x, 0x0000004d;
+		imm32 R3, 0xae387ec2;
+		imm32 R4, 0x7fff99ff;
+		imm32 R5, 0x46730cf4;
+	R5 = (A1 += R4.L * R3.H) (M, IU);
+		checkreg R5, 0x7fffffff;
+		checkreg A1.w, 0xf3b41d84;
+		checkreg A1.x, 0x0000004c;
+		checkreg ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x60d00200 | _VS | _AV1S | _CC);
+	dmm32 A1.w, 0x002b5780;
+	dmm32 A1.x, 0x00000000;
+		imm32 R1, 0xa07dffff;
+		imm32 R2, 0xf90db994;
+		imm32 R4, 0x46150060;
+	R2.H = (A1 -= R1.L * R4.L) (M, IU);
+		checkreg R2, 0x7fffb994;
+		checkreg A1.w, 0x002b57e0;
+		checkreg A1.x, 0x00000000;
+		checkreg ASTAT, (0x60d00200 | _VS | _V | _AV1S | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV1 | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x52768086;
+	dmm32 A1.x, 0x00000035;
+		imm32 R2, 0x1e89d049;
+		imm32 R6, 0x5312dd14;
+		imm32 R7, 0x02e3d1f4;
+	R7 = (A1 += R2.L * R6.L) (M, IU);
+		checkreg R7, 0x7fffffff;
+		checkreg A1.w, 0x2941cb3a;
+		checkreg A1.x, 0x00000035;
+		checkreg ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
+	dmm32 A1.w, 0x00005d96;
+	dmm32 A1.x, 0x00000000;
+		imm32 R1, 0x00006828;
+		imm32 R5, 0xfffe5480;
+		imm32 R7, 0x40000009;
+	R5 = (A1 -= R1.L * R7.H) (M, IU);
+		checkreg R5, 0xe5f65d96;
+		checkreg A1.w, 0xe5f65d96;
+		checkreg A1.x, 0xffffffff;
+		checkreg ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x3cb08080 | _VS | _AC1 | _CC | _AC0_COPY | _AZ);
+	dmm32 A1.w, 0x8b063fca;
+	dmm32 A1.x, 0xffffffa2;
+		imm32 R3, 0x5f5b566b;
+		imm32 R4, 0x800022e6;
+		imm32 R5, 0x741acdad;
+	R3 = (A1 += R5.L * R4.L) (M, IU);
+		checkreg R3, 0x80000000;
+		checkreg A1.w, 0x842a0338;
+		checkreg A1.x, 0xffffffa2;
+		checkreg ASTAT, (0x3cb08080 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x60d08a00 | _VS | _AC0 | _AQ | _AN);
+	dmm32 A1.w, 0x54eebd9e;
+	dmm32 A1.x, 0x00000000;
+		imm32 R5, 0x05fa881c;
+		imm32 R7, 0xb0728448;
+	R5 = (A1 -= R7.L * R5.L) (M, IU);
+		checkreg R5, 0x7fffffff;
+		checkreg A1.w, 0x96b605be;
+		checkreg A1.x, 0x00000000;
+		checkreg ASTAT, (0x60d08a00 | _VS | _V | _AC0 | _AQ | _V_COPY | _AN);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0021.S b/sim/testsuite/sim/bfin/random_0021.S
new file mode 100644
index 0000000..2497a44
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0021.S
@@ -0,0 +1,45 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x5c604280 | _VS | _AV1S | _AV0S);
+	imm32 R3, 0xfe0103fe;
+	imm32 R5, 0x1e53cdd8;
+	R3.H = R5.L * R3.H (M, IU);
+	checkreg R3, 0x800003fe;
+	checkreg ASTAT, (0x5c604280 | _VS | _V | _AV1S | _AV0S | _V_COPY);
+
+	dmm32 ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN);
+	imm32 R4, 0xfffeffff;
+	imm32 R5, 0x174e174e;
+	R5.H = R4.L * R5.H (M, IU);
+	checkreg R5, 0xe8b2174e;
+	checkreg ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN);
+
+	dmm32 ASTAT, (0x34308890 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN);
+	imm32 R3, 0x7fffffff;
+	imm32 R4, 0x077b8000;
+	imm32 R7, 0x03bd03bd;
+	R3.H = R4.L * R7.H (M, IU);
+	checkreg R3, 0x8000ffff;
+	checkreg ASTAT, (0x34308890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x58700a90 | _VS | _AV1S | _AC1 | _AQ | _CC | _AN);
+	imm32 R1, 0x58978212;
+	imm32 R3, 0x62b5775a;
+	imm32 R6, 0x4c9c9ee3;
+	R6.H = R1.L * R3.L (M, IU);
+	checkreg R6, 0x80009ee3;
+	checkreg ASTAT, (0x58700a90 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x40204e00 | _VS | _AV1S | _AV0S | _CC | _AN);
+	imm32 R3, 0x297fee00;
+	imm32 R5, 0x79aa9d21;
+	imm32 R6, 0xfffe7484;
+	R6.H = R5.L * R3.L (M, IU);
+	checkreg R6, 0x80007484;
+	checkreg ASTAT, (0x40204e00 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0022.S b/sim/testsuite/sim/bfin/random_0022.S
new file mode 100644
index 0000000..fce2803
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0022.S
@@ -0,0 +1,212 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x2090c600 | _VS | _AC1 | _AQ | _CC | _AN);
+	dmm32 A0.w, 0xf041e418;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R4, 0x51296cc2;
+	imm32 R7, 0xca05cb74;
+	R4.L = (A0 += R7.H * R4.L) (TFU);
+	checkreg R4, 0x5129ffff;
+	checkreg A0.w, 0xffffffff;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x2090c600 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x68508090 | _VS | _AV0S | _AC1 | _AC0_COPY);
+	dmm32 A1.w, 0xf934c2ea;
+	dmm32 A1.x, 0xffffffff;
+	imm32 R0, 0x4c8c85a2;
+	imm32 R1, 0x13507fff;
+	imm32 R7, 0x1bd0df6a;
+	R0.H = (A1 += R7.L * R1.L) (TFU);
+	checkreg R0, 0xffff85a2;
+	checkreg A1.w, 0xffffffff;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x68508090 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x54e0c200 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY);
+	dmm32 A0.w, 0xed4a5c88;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R1, 0x1332a428;
+	imm32 R4, 0x59fd2452;
+	imm32 R6, 0x001fffc3;
+	R4.L = (A0 += R1.H * R6.L) (TFU);
+	checkreg R4, 0x59fdffff;
+	checkreg A0.w, 0xffffffff;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x54e0c200 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x70500000 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN);
+	dmm32 A0.w, 0xb959adf4;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R0, 0xffc20000;
+	imm32 R4, 0x9b83ffff;
+	R0.L = (A0 += R4.L * R4.H) (TFU);
+	checkreg R0, 0xffc2ffff;
+	checkreg A0.w, 0xffffffff;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x70500000 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x58f04890 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
+	dmm32 A0.w, 0xfd1277cc;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R5, 0xfffdffe2;
+	imm32 R7, 0x1a9bcac8;
+	R5.L = (A0 += R5.H * R7.L) (TFU);
+	checkreg R5, 0xfffdffff;
+	checkreg A0.w, 0xffffffff;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x58f04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x2840ce90 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY);
+	dmm32 A1.w, 0x1543f138;
+	dmm32 A1.x, 0xffffffce;
+	imm32 R3, 0xf4620000;
+	imm32 R4, 0x80008000;
+	imm32 R7, 0x0d156000;
+	R4.H = (A1 -= R3.L * R7.L) (M, TFU);
+	checkreg R4, 0x80008000;
+	checkreg A1.w, 0x1543f138;
+	checkreg A1.x, 0xffffffce;
+	checkreg ASTAT, (0x2840ce90 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x04000c90 | _AV0S | _AC0 | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x7c7b42a9;
+	dmm32 A1.x, 0x00000027;
+	imm32 R2, 0x28454c31;
+	imm32 R5, 0xf220f1b0;
+	imm32 R6, 0x257ab18b;
+	R2.H = (A1 -= R5.L * R6.L) (M, TFU);
+	checkreg R2, 0x7fff4c31;
+	checkreg A1.w, 0x86685819;
+	checkreg A1.x, 0x00000027;
+	checkreg ASTAT, (0x04000c90 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x6810ce80 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x00000000;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x00008000;
+	imm32 R6, 0x5857bcbe;
+	R6.H = (A1 = R6.L * R0.L) (M, TFU);
+	checkreg R6, 0xde5fbcbe;
+	checkreg A1.w, 0xde5f0000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x6810ce80 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x78c00c80 | _VS | _V | _AC0 | _V_COPY | _AN);
+	dmm32 A1.w, 0x63391186;
+	dmm32 A1.x, 0x0000005e;
+	imm32 R2, 0x34a8b6ef;
+	imm32 R7, 0x7c8142e2;
+	R7.H = (A1 = R2.L * R2.H) (M, TFU);
+	checkreg R7, 0xf0f842e2;
+	checkreg A1.w, 0xf0f898d8;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x78c00c80 | _VS | _AC0 | _AN);
+
+	dmm32 ASTAT, (0x70704410 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0x3fff0001;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0xffffffff;
+	imm32 R7, 0x80007fff;
+	R7.H = (A1 = R0.L * R7.L) (M, TFU);
+	checkreg R7, 0xffff7fff;
+	checkreg A1.w, 0xffff8001;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x70704410 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
+
+	dmm32 ASTAT, (0x00b08610 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xe75e6c55;
+	dmm32 A1.x, 0xffffffff;
+	imm32 R1, 0x5073b60d;
+	imm32 R3, 0x1c5eecaf;
+	R1.H = (A1 = R3.L * R3.H) (M, TFU);
+	checkreg R1, 0xfddcb60d;
+	checkreg A1.w, 0xfddc0c42;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x00b08610 | _VS | _AV1S | _AV0S | _AV0 | _AQ | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x00304690 | _AV1 | _AV0S | _AV0 | _AQ | _AZ);
+	dmm32 A1.w, 0x2ef1b58e;
+	dmm32 A1.x, 0xffffffd7;
+	imm32 R3, 0x37807856;
+	imm32 R4, 0x2cd7d02c;
+	imm32 R5, 0x4435ba51;
+	R4.H = (A1 -= R3.L * R5.L) (M, TFU);
+	checkreg R4, 0x8000d02c;
+	checkreg A1.w, 0xd75d2658;
+	checkreg A1.x, 0xffffffd6;
+	checkreg ASTAT, (0x00304690 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ);
+
+	dmm32 ASTAT, (0x74c0c600 | _VS | _AV1 | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x4325067d;
+	dmm32 A1.x, 0xffffffee;
+	imm32 R0, 0x35ca7288;
+	imm32 R5, 0x5ec6e257;
+	R0.H = (A1 += R0.L * R5.H) (M, TFU);
+	checkreg R0, 0x80007288;
+	checkreg A1.w, 0x6d8b8bad;
+	checkreg A1.x, 0xffffffee;
+	checkreg ASTAT, (0x74c0c600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x50704690 | _VS | _AQ);
+	dmm32 A1.w, 0xd0cea2a8;
+	dmm32 A1.x, 0xffffffff;
+	imm32 R0, 0x11b4e24e;
+	imm32 R2, 0xecd6793c;
+	imm32 R7, 0x329c2dd6;
+	R0.H = (A1 -= R7.L * R2.L) (M, TFU);
+	checkreg R0, 0xbb19e24e;
+	checkreg A1.w, 0xbb19be80;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x50704690 | _VS | _AQ);
+
+	dmm32 ASTAT, (0x10d08000 | _VS | _AC1 | _AN);
+	dmm32 A1.w, 0x32dd86a1;
+	dmm32 A1.x, 0xffffffd7;
+	imm32 R1, 0xb2310000;
+	imm32 R3, 0xd63992d2;
+	imm32 R5, 0x2b93b27f;
+	R5.H = (A1 += R3.L * R1.L) (M, TFU);
+	checkreg R5, 0x8000b27f;
+	checkreg A1.w, 0x32dd86a1;
+	checkreg A1.x, 0xffffffd7;
+	checkreg ASTAT, (0x10d08000 | _VS | _V | _AC1 | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x3010c600 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0xf99eabd6;
+	dmm32 A1.x, 0xffffffff;
+	imm32 R2, 0x0c196618;
+	imm32 R5, 0x00008000;
+	imm32 R6, 0x6617ffff;
+	R5.H = (A1 -= R6.L * R2.L) (M, TFU);
+	checkreg R5, 0xf99f8000;
+	checkreg A1.w, 0xf99f11ee;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x3010c600 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _AC0_COPY);
+
+	dmm32 ASTAT, (0x30f0ca80 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AN);
+	dmm32 A0.w, 0x74ea7d56;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R0, 0x29abffff;
+	imm32 R2, 0xade1ffff;
+	imm32 R7, 0x20ada3b8;
+	R0.L = (A0 += R2.L * R7.L) (TFU);
+	checkreg A0.w, 0xffffffff;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x30f0ca80 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x48608210 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN);
+	dmm32 A0.w, 0x120f0000;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R3, 0xfeacf0c4;
+	R3.L = (A0 += R3.H * R3.H) (TFU);
+	checkreg R3, 0xfeacffff;
+	checkreg A0.w, 0xffffffff;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x48608210 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY | _AN);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0023.S b/sim/testsuite/sim/bfin/random_0023.S
new file mode 100644
index 0000000..9dd2d1a
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0023.S
@@ -0,0 +1,97 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0xf41fbf3f;
+	dmm32 A1.x, 0x00000000;
+	imm32 R5, 0xd8d95310;
+	imm32 R6, 0xd0457fff;
+	R5.H = (A1 -= R6.L * R6.H) (M, FU);
+	checkreg R5, 0x7fff5310;
+	checkreg A1.w, 0x8bfe0f84;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x54b0ca90 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xf88288c8;
+	dmm32 A1.x, 0xffffffff;
+	imm32 R0, 0xfffe6736;
+	imm32 R2, 0x8000f882;
+	imm32 R3, 0xffff8391;
+	R0.H = (A1 += R3.L * R2.L) (M, FU);
+	checkreg R0, 0x80006736;
+	checkreg A1.w, 0x7fb7d06a;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x54b0ca90 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x1c500480 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x9083dd08;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x00000000;
+	imm32 R4, 0x00002492;
+	R4.H = (A1 += R4.L * R0.H) (M, FU);
+	checkreg R4, 0x7fff2492;
+	checkreg ASTAT, (0x1c500480 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x7c00c810 | _AV1S | _AC1 | _AC0);
+	dmm32 A1.w, 0x69e86d3f;
+	dmm32 A1.x, 0xffffffc2;
+	imm32 R1, 0x64f42c5b;
+	imm32 R3, 0x4128529d;
+	R3 = (A1 -= R3.L * R1.L) (M, FU);
+	checkreg R3, 0x80000000;
+	checkreg A1.w, 0x5b981370;
+	checkreg A1.x, 0xffffffc2;
+	checkreg ASTAT, (0x7c00c810 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY);
+
+	dmm32 ASTAT, (0x5cc0c480 | _VS | _AQ | _CC);
+	dmm32 A1.w, 0x34bbe964;
+	dmm32 A1.x, 0x00000036;
+	imm32 R1, 0x7fffffff;
+	imm32 R5, 0x7fff427e;
+	A1 -= R5.L * R1.L (M, FU);
+	checkreg A1.w, 0xf23e2be2;
+	checkreg A1.x, 0x00000035;
+	checkreg ASTAT, (0x5cc0c480 | _VS | _AQ | _CC);
+
+# here the result is zero, and the _V bit is set
+	dmm32 ASTAT, 0x0;
+	dmm32 A0.w, 0x00008492;
+	dmm32 A0.x, 0x00000000;
+	imm32 R2, 0x7fff0002;
+	imm32 R3, 0xfa6e8492;
+	imm32 R6, 0xffff0002;
+	R6 = (A0 -= R3.L * R2.L) (FU);
+	checkreg R6, 0x00000000;
+	checkreg A0.w, 0x00000000;
+	checkreg A0.x, 0x00000000;
+	checkreg ASTAT, ( _VS | _V | _AV0S | _AV0 | _V_COPY);
+
+# here the result is zero, and the _V bit is not set
+	dmm32 ASTAT, (_V | _V_COPY);
+	dmm32 A0.w, 0x1fffc000;
+	dmm32 A0.x, 0x00000000;
+	imm32 R0, 0x80004000;
+	imm32 R4, 0x1fffffff;
+	imm32 R6, 0x80000000;
+	R4.L = (A0 -= R0.L * R6.H) (FU);
+	checkreg R4, 0x1fff0000;
+	checkreg A0.w, 0x00000000;
+	checkreg A0.x, 0x00000000;
+	checkreg ASTAT, (_AV0S | _AV0);
+
+	dmm32 ASTAT, (0x0c108610 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
+	dmm32 A0.w, 0x0000eaf0;
+	dmm32 A0.x, 0x00000000;
+	imm32 R1, 0x00010000;
+	imm32 R6, 0xfbf10001;
+	R1.L = (A0 -= R6.H * R1.H) (FU);
+	checkreg R1, 0x00010000;
+	checkreg A0.w, 0x00000000;
+	checkreg A0.x, 0x00000000;
+	checkreg ASTAT, (0x0c108610 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0024.S b/sim/testsuite/sim/bfin/random_0024.S
new file mode 100644
index 0000000..dab8880
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0024.S
@@ -0,0 +1,264 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ);
+	imm32 R2, 0x00000000;
+	imm32 R4, 0x00000000;
+	imm32 R7, 0x00000000;
+	R2 = ASHIFT R7 BY R4.L (S);
+	checkreg ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ);
+	checkreg R2, 0x00000000;
+	checkreg R4, 0x00000000;
+	checkreg R7, 0x00000000;
+
+	dmm32 ASTAT, (0x7c104680 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ);
+	imm32 R7, 0x00000000;
+	R7 = R7 << 0xe (S);
+	checkreg R7, 0x00000000;
+	checkreg ASTAT, (0x7c104680 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x10d08690 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
+	imm32 R2, 0x0000ffff;
+	imm32 R5, 0x00000000;
+	R2 = R5 << 0x1a (S);
+	checkreg R2, 0x00000000;
+	checkreg ASTAT, (0x10d08690 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x30f08e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
+	imm32 R6, 0x00000000;
+	R6 = ASHIFT R6 BY R6.L (S);
+	checkreg ASTAT, (0x30f08e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
+	checkreg R6, 0x00000000;
+
+	dmm32 ASTAT, (0x4060c800 | _VS | _AV0S | _AC1 | _CC | _AZ);
+	imm32 R5, 0x00000000;
+	imm32 R7, 0x00000000;
+	R5 = R7 << 0x15 (S);
+	checkreg ASTAT, (0x4060c800 | _VS | _AV0S | _AC1 | _CC | _AZ);
+	checkreg R5, 0x00000000;
+	checkreg R7, 0x00000000;
+
+	dmm32 ASTAT, (0x78604a10 | _VS | _AN);
+	imm32 R1, 0x00000000;
+	imm32 R4, 0xe1a88000;
+	R4 = R1 << 0xb (S);
+	checkreg R4, 0x00000000;
+	checkreg ASTAT, (0x78604a10 | _VS | _AZ);
+
+	dmm32 ASTAT, (0x64304800 | _VS | _AV1S | _AV0S | _AC0_COPY);
+	imm32 R2, 0x00000000;
+	imm32 R7, 0x00000000;
+	R7 = R2 << 0xa (S);
+	checkreg ASTAT, (0x64304800 | _VS | _AV1S | _AV0S | _AC0_COPY | _AZ);
+	checkreg R2, 0x00000000;
+	checkreg R7, 0x00000000;
+
+	dmm32 ASTAT, (0x68f0c280 | _VS | _AC1 | _AC0_COPY | _AN);
+	imm32 R2, 0x00000000;
+	imm32 R5, 0x0000f74a;
+	R5 = R2 << 0x10 (S);
+	checkreg R5, 0x00000000;
+	checkreg ASTAT, (0x68f0c280 | _VS | _AC1 | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x54200c80 | _VS | _AV1S | _AV0S | _AQ);
+	imm32 R1, 0x00000000;
+	imm32 R2, 0x00000000;
+	R2 = R1 << 0xa (S);
+	checkreg ASTAT, (0x54200c80 | _VS | _AV1S | _AV0S | _AQ | _AZ);
+	checkreg R1, 0x00000000;
+	checkreg R2, 0x00000000;
+
+	dmm32 ASTAT, (0x20300a80 | _VS | _AV1S | _CC | _AZ);
+	imm32 R2, 0x00000000;
+	imm32 R7, 0x00000000;
+	R7 = R2 << 0x8 (S);
+	checkreg ASTAT, (0x20300a80 | _VS | _AV1S | _CC | _AZ);
+	checkreg R2, 0x00000000;
+	checkreg R7, 0x00000000;
+
+	dmm32 ASTAT, (0x14408e10 | _VS | _AV0S | _AQ | _CC | _AZ);
+	imm32 R4, 0x0000007f;
+	imm32 R6, 0x00000000;
+	R4 = R6 << 0x3 (S);
+	checkreg R4, 0x00000000;
+	checkreg ASTAT, (0x14408e10 | _VS | _AV0S | _AQ | _CC | _AZ);
+
+	dmm32 ASTAT, (0x2850c490 | _VS | _AV1S | _AV0S | _AZ);
+	imm32 R5, 0x00000000;
+	imm32 R7, 0xf67f0000;
+	R7 = ASHIFT R5 BY R7.L (S);
+	checkreg R7, 0x00000000;
+	checkreg ASTAT, (0x2850c490 | _VS | _AV1S | _AV0S | _AZ);
+
+	dmm32 ASTAT, (0x24a00400 | _VS | _AV1S | _AC0 | _AC0_COPY | _AN);
+	imm32 R4, 0x00001e68;
+	imm32 R6, 0x00000000;
+	R4 = R6 << 0x8 (S);
+	checkreg R4, 0x00000000;
+	checkreg ASTAT, (0x24a00400 | _VS | _AV1S | _AC0 | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x34608e00 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN);
+	imm32 R1, 0x00000000;
+	imm32 R5, 0x272beb60;
+	R5 = R1 << 0xa (S);
+	checkreg R5, 0x00000000;
+	checkreg ASTAT, (0x34608e00 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ);
+
+	dmm32 ASTAT, (0x20800c90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AN);
+	imm32 R3, 0x532993ba;
+	imm32 R5, 0x00000000;
+	R3 = R5 << 0x9 (S);
+	checkreg R3, 0x00000000;
+	checkreg ASTAT, (0x20800c90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x5430c090 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY);
+	imm32 R1, 0xb1510802;
+	imm32 R6, 0x00000000;
+	R1 = R6 << 0x1e (S);
+	checkreg R1, 0x00000000;
+	checkreg ASTAT, (0x5430c090 | _VS | _AV0S | _AC0 | _AQ | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x5cf04c90 | _VS | _AV1S | _AC1 | _AQ | _AC0_COPY);
+	dmm32 A1.w, 0xf9bc55b7;
+	dmm32 A1.x, 0x0000002a;
+	imm32 R0, 0x002d0024;
+	imm32 R1, 0x16970042;
+	A1 += R0.L * R1.L;
+	checkreg A1.w, 0xf9bc6847;
+	checkreg A1.x, 0x0000002a;
+	checkreg ASTAT, (0x5cf04c90 | _VS | _AV1S | _AC1 | _AQ | _AC0_COPY);
+
+	dmm32 ASTAT, (0x7c804090 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
+	imm32 R5, 0x00000000;
+	imm32 R7, 0xfe773828;
+	R7 = R5 << 0x19 (S);
+	checkreg R7, 0x00000000;
+	checkreg ASTAT, (0x7c804090 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x30f04e90 | _VS | _AV0S | _AC0 | _AQ);
+	imm32 R3, 0x00000000;
+	imm32 R7, 0x00000372;
+	R7 = R3 << 0x6 (S);
+	checkreg R7, 0x00000000;
+	checkreg ASTAT, (0x30f04e90 | _VS | _AV0S | _AC0 | _AQ | _AZ);
+
+	dmm32 ASTAT, (0x04708210 | _VS | _AV1S | _AC0 | _AQ | _AN);
+	imm32 R5, 0x00000000;
+	imm32 R7, 0x79b3d220;
+	R7 = R5 << 0x13 (S);
+	checkreg R7, 0x00000000;
+	checkreg ASTAT, (0x04708210 | _VS | _AV1S | _AC0 | _AQ | _AZ);
+
+	dmm32 ASTAT, (0x24e08680 | _VS | _AV0S | _AC1 | _CC | _AZ);
+	imm32 R0, 0x00000000;
+	imm32 R6, 0x00000000;
+	imm32 R7, 0xa820afc0;
+	R6 = ASHIFT R0 BY R7.L (S);
+	checkreg ASTAT, (0x24e08680 | _VS | _AV0S | _AC1 | _CC | _AZ);
+	checkreg R0, 0x00000000;
+	checkreg R6, 0x00000000;
+	checkreg R7, 0xa820afc0;
+
+	dmm32 ASTAT, (0x0ca0c090 | _VS | _AQ | _AZ);
+	imm32 R6, 0x00000000;
+	imm32 R7, 0x0000001f;
+	R7 = R6 << 0x14 (S);
+	checkreg R7, 0x00000000;
+	checkreg ASTAT, (0x0ca0c090 | _VS | _AQ | _AZ);
+
+	dmm32 ASTAT, (0x20204680 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY);
+	imm32 R6, 0x00000000;
+	R6 = R6 << 0x15 (S);
+	checkreg ASTAT, (0x20204680 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AZ);
+	checkreg R6, 0x00000000;
+
+	dmm32 ASTAT, (0x14f08c00 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ);
+	imm32 R2, 0x00000000;
+	imm32 R6, 0x00007fff;
+	R6 = R2 << 0x1b (S);
+	checkreg R6, 0x00000000;
+	checkreg ASTAT, (0x14f08c00 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x50b08c00 | _VS | _AC1 | _AQ | _CC | _AN);
+	imm32 R1, 0x00000000;
+	imm32 R4, 0x0000fffd;
+	R4 = R1 << 0x9 (S);
+	checkreg R4, 0x00000000;
+	checkreg ASTAT, (0x50b08c00 | _VS | _AC1 | _AQ | _CC | _AZ);
+
+	dmm32 ASTAT, (0x1cb04200 | _VS | _AV0S | _AC1 | _CC);
+	imm32 R0, 0x00000000;
+	imm32 R2, 0xdeab0000;
+	R2 = R0 << 0x1e (S);
+	checkreg R2, 0x00000000;
+	checkreg ASTAT, (0x1cb04200 | _VS | _AV0S | _AC1 | _CC | _AZ);
+
+	dmm32 ASTAT, (0x54c0ca00 | _VS | _AV1S | _AV0S | _AC1);
+	imm32 R6, 0x00000000;
+	imm32 R7, 0x9ec9c597;
+	R7 = R6 << 0x8 (S);
+	checkreg R7, 0x00000000;
+	checkreg ASTAT, (0x54c0ca00 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
+
+	dmm32 ASTAT, (0x18804400 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AN);
+	imm32 R7, 0x00000000;
+	R7 = R7 << 0x1d (S);
+	checkreg ASTAT, (0x18804400 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ);
+	checkreg R7, 0x00000000;
+
+	dmm32 ASTAT, (0x40c08e90 | _VS | _AV1S | _AV0S | _CC);
+	imm32 R2, 0x00000000;
+	imm32 R5, 0x80000000;
+	imm32 R7, 0x00000000;
+	R5 = ASHIFT R2 BY R7.L (S);
+	checkreg R5, 0x00000000;
+	checkreg ASTAT, (0x40c08e90 | _VS | _AV1S | _AV0S | _CC | _AZ);
+
+	dmm32 ASTAT, (0x70b04290 | _VS | _AV1S | _AV0S | _AQ | _AZ);
+	imm32 R5, 0x8000c2d0;
+	imm32 R6, 0x00000000;
+	R5 = R6 << 0x2 (S);
+	checkreg R5, 0x00000000;
+	checkreg ASTAT, (0x70b04290 | _VS | _AV1S | _AV0S | _AQ | _AZ);
+
+	dmm32 ASTAT, (0x7cf04480 | _VS | _AV0S | _AC0 | _AC0_COPY | _AZ);
+	imm32 R3, 0x00000000;
+	imm32 R7, 0x00000000;
+	R7 = ASHIFT R3 BY R7.L (S);
+	checkreg ASTAT, (0x7cf04480 | _VS | _AV0S | _AC0 | _AC0_COPY | _AZ);
+	checkreg R3, 0x00000000;
+	checkreg R7, 0x00000000;
+
+	dmm32 ASTAT, (0x78d0c290 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
+	imm32 R1, 0x7c98345a;
+	imm32 R4, 0x00000000;
+	R1 = ASHIFT R4 BY R1.L (S);
+	checkreg R1, 0x00000000;
+	checkreg ASTAT, (0x78d0c290 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x58400e80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY);
+	imm32 R2, 0x00000000;
+	imm32 R4, 0x7fffffff;
+	R4 = R2 << 0x8 (S);
+	checkreg R4, 0x00000000;
+	checkreg ASTAT, (0x58400e80 | _VS | _AV0S | _AQ | _CC | _AZ);
+
+	dmm32 ASTAT, (0x4c804080 | _VS | _V | _AV1S | _AV0S | _AV0 | _V_COPY);
+	imm32 R3, 0x00000000;
+	imm32 R7, 0x3d196b66;
+	R7 = ASHIFT R3 BY R3.L (S);
+	checkreg R7, 0x00000000;
+	checkreg ASTAT, (0x4c804080 | _VS | _AV1S | _AV0S | _AV0 | _AZ);
+
+	dmm32 ASTAT, (0x44304a10 | _VS | _AV0S | _AQ | _AZ);
+	imm32 R4, 0x00000000;
+	imm32 R6, 0x00000000;
+	R6 = R4 << 0x11 (S);
+	checkreg ASTAT, (0x44304a10 | _VS | _AV0S | _AQ | _AZ);
+	checkreg R4, 0x00000000;
+	checkreg R6, 0x00000000;
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0026.S b/sim/testsuite/sim/bfin/random_0026.S
new file mode 100644
index 0000000..526b007
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0026.S
@@ -0,0 +1,195 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x4c60c810 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
+	dmm32 A0.w, 0x7fffffff;
+	dmm32 A0.x, 0x00000000;
+	imm32 R0, 0x00000000;
+	imm32 R5, 0x00007fff;
+	imm32 R7, 0x00000000;
+	R7.L = (A0 += R0.L * R5.L) (IH);
+	checkreg R7, 0x00007fff;
+	checkreg A0.w, 0x7fffffff;
+	checkreg A0.x, 0x00000000;
+	checkreg ASTAT, (0x4c60c810 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x00500680 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN);
+	dmm32 A0.w, 0x80000000;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R2, 0xffffffff;
+	imm32 R4, 0xa8dd8000;
+	imm32 R7, 0x80000000;
+	R4.L = (A0 -= R2.L * R7.H) (IH);
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg R4, 0xa8dd8000;
+	checkreg ASTAT, (0x00500680 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x50408c90 | _VS | _V | _AV1S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN);
+	dmm32 A1.w, 0xfa400000;
+	dmm32 A1.x, 0xffffffad;
+	imm32 R0, 0x366b1c84;
+	imm32 R3, 0x7fffffff;
+	imm32 R7, 0x32528aa5;
+	R3.H = (A1 += R0.L * R7.L) (M, IH);
+	checkreg R3, 0x8000ffff;
+	checkreg A1.w, 0x80000000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x50408c90 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x0c400c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xef56cbd3;
+	dmm32 A1.x, 0x00000000;
+	imm32 R3, 0x7fff0003;
+	imm32 R4, 0x385cffff;
+	imm32 R7, 0x680dffff;
+	R7.H = (A1 -= R4.L * R3.H) (M, IH);
+	checkreg R7, 0x7fffffff;
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x0c400c10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x2c604c00 | _AV1S | _AV0 | _AC1);
+	dmm32 A1.w, 0xf54ee9bb;
+	dmm32 A1.x, 0x0000004a;
+	imm32 R3, 0x10bb4bdc;
+	imm32 R4, 0x7f29c57d;
+	imm32 R7, 0x2c03f00a;
+	R4.H = (A1 -= R3.L * R7.H) (M, IH);
+	checkreg R4, 0x7fffc57d;
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x2c604c00 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC1 | _V_COPY);
+
+	dmm32 ASTAT, (0x2c304800 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY);
+	dmm32 A1.w, 0xc1a6b608;
+	dmm32 A1.x, 0x00000056;
+	imm32 R2, 0xd0457fff;
+	imm32 R6, 0xf4b2ffff;
+	R6.H = (A1 += R2.L * R6.H) (M, IH);
+	checkreg R6, 0x7fffffff;
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x2c304800 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY);
+
+	dmm32 ASTAT, (0x04a08810 | _VS | _AV1S | _AC1 | _AC0 | _AN);
+	dmm32 A1.w, 0xe9574334;
+	dmm32 A1.x, 0x00000056;
+	imm32 R3, 0xffffb2bc;
+	imm32 R5, 0x03eb4d44;
+	imm32 R6, 0x33852750;
+	R5.H = (A1 -= R6.L * R3.L) (M, IH);
+	checkreg R5, 0x7fff4d44;
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x04a08810 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x5860c210 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY);
+	dmm32 A1.w, 0xd5030654;
+	dmm32 A1.x, 0x0000001c;
+	imm32 R0, 0x20ccb6ee;
+	imm32 R2, 0x74c21675;
+	imm32 R4, 0x7fff7fff;
+	R2.H = (A1 -= R0.L * R4.L) (M, IH);
+	checkreg R2, 0x7fff1675;
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x5860c210 | _VS | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY);
+
+	dmm32 ASTAT, (0x34800e00 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xf0b59d3f;
+	dmm32 A1.x, 0xffffffef;
+	imm32 R4, 0x28bd7772;
+	imm32 R6, 0xef66ce6a;
+	imm32 R7, 0x80000000;
+	R6.H = (A1 -= R4.L * R7.H) (M, IH);
+	checkreg R6, 0x8000ce6a;
+	checkreg A1.w, 0x80000000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x34800e00 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x5c804a90 | _VS | _AV1S | _AV0S | _AQ | _AN);
+	dmm32 A1.w, 0xc90d8c2f;
+	dmm32 A1.x, 0xffffffee;
+	imm32 R0, 0x80006a2f;
+	imm32 R3, 0x80000000;
+	R3.H = (A1 += R0.L * R0.H) (M, IH);
+	checkreg A1.w, 0x80000000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x5c804a90 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x5c90c010 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN);
+	dmm32 A1.w, 0x80ca2186;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0xf3ec0000;
+	imm32 R3, 0x5a859a0a;
+	imm32 R6, 0x19e852d9;
+	R3.H = (A1 -= R1.L * R6.L) (M, IH);
+	checkreg R3, 0x7fff9a0a;
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x5c90c010 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC0 | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x00f00a10 | _VS | _V | _AV0S | _CC | _V_COPY | _AN);
+	dmm32 A1.w, 0x9f5baab0;
+	dmm32 A1.x, 0x00000019;
+	imm32 R1, 0x1bb2489b;
+	imm32 R6, 0x0aa80127;
+	R1.H = (A1 -= R6.L * R6.H) (M, IH);
+	checkreg R1, 0x7fff489b;
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x00f00a10 | _VS | _V | _AV1S | _AV1 | _AV0S | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x3c808210 | _VS | _V | _AV1S | _V_COPY | _AN);
+	dmm32 A1.w, 0xe09f1e24;
+	dmm32 A1.x, 0x00000025;
+	imm32 R1, 0x255b55bc;
+	imm32 R2, 0x7f1bd115;
+	imm32 R3, 0xbc978902;
+	R2.H = (A1 -= R3.L * R1.H) (M, IH);
+	checkreg R2, 0x7fffd115;
+	checkreg A1.w, 0x7fffffff;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x3c808210 | _VS | _V | _AV1S | _AV1 | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x1ca04600 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0xb80e1ddd;
+	dmm32 A1.x, 0xffffffca;
+	imm32 R0, 0x2155a4b5;
+	imm32 R1, 0x5dd905c2;
+	imm32 R2, 0x769083dc;
+	R1.H = (A1 -= R2.L * R0.H) (M, IH);
+	checkreg R1, 0x800005c2;
+	checkreg A1.w, 0x80000000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x1ca04600 | _VS | _V | _AV1S | _AV1 | _AV0S | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x1cb0cc90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xfc7c3973;
+	dmm32 A1.x, 0xffffff8a;
+	imm32 R1, 0x58a6c4e7;
+	imm32 R4, 0x19b16033;
+	imm32 R6, 0x301ff2ba;
+	R6.H = (A1 -= R4.L * R1.H) (M, IH);
+	checkreg R6, 0x8000f2ba;
+	checkreg A1.w, 0x80000000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x1cb0cc90 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x2c800810 | _VS | _AV1S | _AQ | _CC | _AN);
+	dmm32 A1.w, 0xd86a7676;
+	dmm32 A1.x, 0xffffff97;
+	imm32 R3, 0x443fea83;
+	imm32 R4, 0x47ed4ac3;
+	imm32 R6, 0x7fffffff;
+	R4.H = (A1 += R3.L * R6.L) (M, IH);
+	checkreg R4, 0x80004ac3;
+	checkreg A1.w, 0x80000000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x2c800810 | _VS | _V | _AV1S | _AV1 | _AQ | _CC | _V_COPY | _AN);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0027.S b/sim/testsuite/sim/bfin/random_0027.S
new file mode 100644
index 0000000..06ea3c8
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0027.S
@@ -0,0 +1,266 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x2850c890 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY);
+	dmm32 A1.w, 0xa605868e;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0x56dd0982;
+	imm32 R4, 0x50e37862;
+	imm32 R5, 0x597fc81a;
+	R4.H = (A1 -= R5.L * R1.L) (M, IS);
+	checkreg R4, 0x7fff7862;
+	checkreg A1.w, 0xa818ff5a;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x2850c890 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x08100a00 | _VS | _AC1 | _AC0 | _CC);
+	dmm32 A1.w, 0xeb710132;
+	dmm32 A1.x, 0xffffffcf;
+	imm32 R4, 0x750d92cc;
+	imm32 R7, 0xf9a22cee;
+	R4.H = (A1 -= R7.L * R7.H) (M, IS);
+	checkreg R4, 0x800092cc;
+	checkreg A1.w, 0xbfa11496;
+	checkreg A1.x, 0xffffffcf;
+	checkreg ASTAT, (0x08100a00 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x44e00410 | _VS | _AV0S | _AQ | _AN);
+	dmm32 A1.w, 0x95489ea8;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0x360dca41;
+	imm32 R4, 0x7fffe848;
+	imm32 R7, 0x278abda8;
+	R7 = (A1 -= R4.L * R1.L) (M, IS);
+	checkreg R7, 0x7fffffff;
+	checkreg A1.w, 0xa805d460;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x44e00410 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
+	dmm32 A1.w, 0xcfa4f43b;
+	dmm32 A1.x, 0x0000006c;
+	imm32 R3, 0x0903dd55;
+	imm32 R7, 0x7fffc2b1;
+	A1 -= R3.L * R7.L (M, IS);
+	checkreg A1.w, 0xea028276;
+	checkreg A1.x, 0x0000006c;
+	checkreg ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x3c204410 | _VS | _AV0S | _AN);
+	dmm32 A1.w, 0x928b984e;
+	dmm32 A1.x, 0xffffffd5;
+	imm32 R5, 0x00003ddd;
+	imm32 R7, 0x8000ffff;
+	A1 += R5.L * R7.L (M, IS);
+	checkreg A1.w, 0xd0685a71;
+	checkreg A1.x, 0xffffffd5;
+	checkreg ASTAT, (0x3c204410 | _VS | _AV0S | _AN);
+
+	dmm32 ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x8837abf1;
+	dmm32 A1.x, 0x00000000;
+	imm32 R3, 0x10c90000;
+	imm32 R7, 0x7fffe6b8;
+	A1 += R7.L * R3.H (M, IS);
+	checkreg A1.w, 0x868f5269;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY);
+	dmm32 A1.w, 0xdca875cf;
+	dmm32 A1.x, 0x0000002c;
+	imm32 R3, 0x4c0892ef;
+	imm32 R5, 0x001fea98;
+	R5.H = (A1 += R5.L * R3.H) (M, IS);
+	checkreg R5, 0x7fffea98;
+	checkreg A1.w, 0xd64cea8f;
+	checkreg A1.x, 0x0000002c;
+	checkreg ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xec5ef880;
+	dmm32 A1.x, 0xfffffffe;
+	imm32 R0, 0x229657d6;
+	imm32 R7, 0xedd48000;
+	A1 += R0.L * R7.L (M, IS);
+	checkreg A1.w, 0x1849f880;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
+	dmm32 A1.w, 0xe4a5a6e1;
+	dmm32 A1.x, 0x00000078;
+	imm32 R0, 0xf059329d;
+	imm32 R7, 0x7fff7512;
+	A1 += R7.L * R0.L (M, IS);
+	checkreg A1.w, 0xfbcaf6eb;
+	checkreg A1.x, 0x00000078;
+	checkreg ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
+
+	dmm32 ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ);
+	dmm32 A1.w, 0xd56a8232;
+	dmm32 A1.x, 0x00000033;
+	imm32 R0, 0x09b22c69;
+	imm32 R7, 0x434f1d64;
+	A1 -= R0.L * R7.L (M, IS);
+	checkreg A1.w, 0xd051442e;
+	checkreg A1.x, 0x00000033;
+	checkreg ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x86c9a59e;
+	dmm32 A1.x, 0xffffff9a;
+	imm32 R1, 0x22573f31;
+	imm32 R6, 0x2d0c0155;
+	A1 += R1.L * R6.H (M, IS);
+	checkreg A1.w, 0x91e838ea;
+	checkreg A1.x, 0xffffff9a;
+	checkreg ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xc5c840aa;
+	dmm32 A1.x, 0x00000000;
+	imm32 R4, 0xffff7fff;
+	imm32 R7, 0x658e833f;
+	A1 -= R7.L * R4.H (M, IS);
+	checkreg A1.w, 0x4288c3e9;
+	checkreg A1.x, 0x00000001;
+	checkreg ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN);
+	dmm32 A1.w, 0xf1000000;
+	dmm32 A1.x, 0x00000040;
+	imm32 R3, 0x0cd4edf1;
+	imm32 R6, 0x4dfc08b8;
+	R6.H = (A1 += R6.L * R3.H) (M, IS);
+	checkreg R6, 0x7fff08b8;
+	checkreg A1.w, 0xf16fd860;
+	checkreg A1.x, 0x00000040;
+	checkreg ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x7c004690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xd4deb886;
+	dmm32 A1.x, 0x00000001;
+	imm32 R1, 0x80008000;
+	imm32 R6, 0x22fb6e50;
+	imm32 R7, 0x3fcb147f;
+	R1.H = (A1 -= R7.L * R6.L) (M, IS);
+	checkreg R1, 0x7fff8000;
+	checkreg A1.w, 0xcc09bed6;
+	checkreg A1.x, 0x00000001;
+	checkreg ASTAT, (0x7c004690 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
+	dmm32 A1.w, 0x9698e35b;
+	dmm32 A1.x, 0xfffffffc;
+	imm32 R5, 0x8000038c;
+	imm32 R6, 0x3152ffff;
+	A1 -= R6.L * R5.L (M, IS);
+	checkreg A1.w, 0x9698e6e7;
+	checkreg A1.x, 0xfffffffc;
+	checkreg ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ);
+	dmm32 A1.w, 0x9b02b9c6;
+	dmm32 A1.x, 0xffffffd4;
+	imm32 R2, 0xff020105;
+	imm32 R3, 0xa8ff8000;
+	R3.H = (A1 -= R2.L * R3.L) (M, IS);
+	checkreg R3, 0x80008000;
+	checkreg A1.w, 0x9a8039c6;
+	checkreg A1.x, 0xffffffd4;
+	checkreg ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x990456b2;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x2b76c7b2;
+	imm32 R3, 0x659803c8;
+	imm32 R7, 0x7fffffff;
+	R3.H = (A1 += R7.L * R0.L) (M, IS);
+	checkreg R3, 0x7fff03c8;
+	checkreg A1.w, 0x99038f00;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY);
+	dmm32 A1.w, 0x95d1d45a;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x4331b012;
+	imm32 R5, 0x7fff8000;
+	A1 -= R0.L * R5.H (M, IS);
+	checkreg A1.w, 0xbdc8846c;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY);
+
+	dmm32 ASTAT, (0x30e04410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC);
+	dmm32 A1.w, 0xcf49e4c9;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0xe968a740;
+	imm32 R3, 0xd7383cd5;
+	imm32 R6, 0x5a87c89b;
+	R1 = (A1 += R3.L * R6.H) (M, IS);
+	checkreg R1, 0x7fffffff;
+	checkreg A1.w, 0xe4ccdb1c;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x30e04410 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY);
+	dmm32 A1.w, 0x8bdaf471;
+	dmm32 A1.x, 0xffffffbd;
+	imm32 R3, 0x728d99b1;
+	imm32 R7, 0x181d83c2;
+	A1 -= R7.L * R3.L (M, IS);
+	checkreg A1.w, 0xd671e94f;
+	checkreg A1.x, 0xffffffbd;
+	checkreg ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY);
+
+	dmm32 ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ);
+	dmm32 A1.w, 0xc1cb8a00;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0xc1e98ea8;
+	imm32 R7, 0x0000961f;
+	A1 -= R7.L * R1.L (M, IS);
+	checkreg A1.w, 0xfccbd3a8;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ);
+
+	dmm32 ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ);
+	dmm32 A1.w, 0xfb328cb4;
+	dmm32 A1.x, 0xffffff9b;
+	imm32 R2, 0x8000ffff;
+	imm32 R3, 0x64d21863;
+	imm32 R6, 0x3b7618a6;
+	R2.H = (A1 += R3.L * R6.H) (M, IS);
+	checkreg A1.w, 0x00dc9b56;
+	checkreg A1.x, 0xffffff9c;
+	checkreg ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ);
+
+	dmm32 ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xbfb4c632;
+	dmm32 A1.x, 0x00000044;
+	imm32 R1, 0x7fffffff;
+	imm32 R3, 0xf3e9182e;
+	imm32 R5, 0x3c94d844;
+	R5.H = (A1 += R1.L * R3.H) (M, IS);
+	checkreg R5, 0x7fffd844;
+	checkreg A1.w, 0xbfb3d249;
+	checkreg A1.x, 0x00000044;
+	checkreg ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
+	dmm32 A1.w, 0x83144651;
+	dmm32 A1.x, 0x00000000;
+	imm32 R3, 0x04d0ffff;
+	imm32 R4, 0x9dc8f8d8;
+	imm32 R7, 0x23180d75;
+	R3 = (A1 += R4.L * R7.L) (M, IS);
+	checkreg R3, 0x7fffffff;
+	checkreg A1.w, 0x82b3f909;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0028.S b/sim/testsuite/sim/bfin/random_0028.S
new file mode 100644
index 0000000..2fd31c9
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0028.S
@@ -0,0 +1,220 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x44004010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY);
+	dmm32 A1.w, 0x851fa4fc;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x00000000;
+	imm32 R2, 0x80000000;
+	imm32 R5, 0x139d77b4;
+	R5.H = (A1 += R2.L * R0.L) (M, S2RND);
+	checkreg R5, 0x7fff77b4;
+	checkreg A1.w, 0x851fa4fc;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x44004010 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x48000600 | _VS | _V | _AV1S | _CC | _V_COPY);
+	dmm32 A1.w, 0xc5ee7420;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0x45f17fff;
+	imm32 R2, 0x00000000;
+	imm32 R4, 0xffffffff;
+	R1 = (A1 -= R2.L * R4.H) (M, S2RND);
+	checkreg R1, 0x7fffffff;
+	checkreg A1.w, 0xc5ee7420;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x48000600 | _VS | _V | _AV1S | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x48500a10 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AZ);
+	dmm32 A1.w, 0x965cddab;
+	dmm32 A1.x, 0x00000063;
+	imm32 R1, 0x1d4cc3e7;
+	imm32 R3, 0xe7ce9d8e;
+	imm32 R6, 0x3cc80b2f;
+	R6.H = (A1 -= R3.L * R1.L) (M, S2RND);
+	checkreg R6, 0x7fff0b2f;
+	checkreg A1.w, 0xe1b28889;
+	checkreg A1.x, 0x00000063;
+	checkreg ASTAT, (0x48500a10 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x44308410 | _VS | _AV0S | _CC | _AN);
+	dmm32 A1.w, 0x92315df7;
+	dmm32 A1.x, 0x0000007e;
+	imm32 R1, 0x9e4b24e0;
+	imm32 R4, 0xe3da8000;
+	imm32 R7, 0x00ba086c;
+	R1.H = (A1 -= R7.L * R4.H) (M, S2RND);
+	checkreg R1, 0x7fff24e0;
+	checkreg A1.w, 0x8ab26dff;
+	checkreg A1.x, 0x0000007e;
+	checkreg ASTAT, (0x44308410 | _VS | _V | _AV0S | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x10a00090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0x8ed084bf;
+	dmm32 A1.x, 0xffffffbe;
+	imm32 R0, 0x8000ffff;
+	imm32 R3, 0xbb4e34ef;
+	imm32 R5, 0x7af8492d;
+	R5 = (A1 += R3.L * R0.L) (M, S2RND);
+	checkreg R5, 0x80000000;
+	checkreg A1.w, 0xc3bf4fd0;
+	checkreg A1.x, 0xffffffbe;
+	checkreg ASTAT, (0x10a00090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x10f04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AN | _AZ);
+	dmm32 A1.w, 0x81becdd8;
+	dmm32 A1.x, 0x00000058;
+	imm32 R2, 0x14946201;
+	imm32 R4, 0x1a162edd;
+	R2.H = (A1 -= R2.L * R4.L) (M, S2RND);
+	checkreg R2, 0x7fff6201;
+	checkreg A1.w, 0x6fce04fb;
+	checkreg A1.x, 0x00000058;
+	checkreg ASTAT, (0x10f04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x20f04c80 | _VS | _AV0S | _AN);
+	dmm32 A1.w, 0xe9cc0041;
+	dmm32 A1.x, 0x00000079;
+	imm32 R1, 0x0f62a5a2;
+	imm32 R3, 0x4e8e9bdd;
+	imm32 R7, 0x6630d991;
+	R1 = (A1 -= R3.L * R7.H) (M, S2RND);
+	checkreg R1, 0x7fffffff;
+	checkreg A1.w, 0x11c4b8d1;
+	checkreg A1.x, 0x0000007a;
+	checkreg ASTAT, (0x20f04c80 | _VS | _V | _AV0S | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x20104e00 | _VS | _AC1 | _AC0 | _AQ | _AN);
+	dmm32 A1.w, 0xadeb5c67;
+	dmm32 A1.x, 0xffffffa6;
+	imm32 R1, 0x07911840;
+	imm32 R7, 0x01070000;
+	R7 = (A1 += R1.L * R7.H) (M, S2RND);
+	checkreg R7, 0x80000000;
+	checkreg A1.w, 0xae044627;
+	checkreg A1.x, 0xffffffa6;
+	checkreg ASTAT, (0x20104e00 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x08e04010 | _VS | _AV0S);
+	dmm32 A1.w, 0xff80f384;
+	dmm32 A1.x, 0x00000003;
+	imm32 R1, 0x00000000;
+	imm32 R2, 0x8000387c;
+	imm32 R3, 0x1e547fff;
+	R2.H = (A1 -= R1.L * R3.L) (M, S2RND);
+	checkreg R2, 0x7fff387c;
+	checkreg A1.w, 0xff80f384;
+	checkreg A1.x, 0x00000003;
+	checkreg ASTAT, (0x08e04010 | _VS | _V | _AV0S | _V_COPY);
+
+	dmm32 ASTAT, (0x0cf08280 | _VS | _AV1S | _AC1 | _CC | _AN);
+	dmm32 A1.w, 0x80000000;
+	dmm32 A1.x, 0xffffff80;
+	imm32 R2, 0xecc35cac;
+	imm32 R4, 0x00007fff;
+	imm32 R7, 0x80000000;
+	R7 = (A1 -= R4.L * R2.L) (M, S2RND);
+	checkreg R7, 0x80000000;
+	checkreg A1.w, 0x51aa5cac;
+	checkreg A1.x, 0xffffff80;
+	checkreg ASTAT, (0x0cf08280 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x40c08090 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xfcbe6525;
+	dmm32 A1.x, 0x00000039;
+	imm32 R0, 0x0003f3c0;
+	imm32 R2, 0xfffffffc;
+	imm32 R6, 0xffff0000;
+	R0.H = (A1 -= R2.L * R6.H) (M, S2RND);
+	checkreg R0, 0x7ffff3c0;
+	checkreg A1.w, 0xfcc26521;
+	checkreg A1.x, 0x00000039;
+	checkreg ASTAT, (0x40c08090 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x00704c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY);
+	dmm32 A1.w, 0xdfbb3c19;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x50407788;
+	imm32 R4, 0x50407788;
+	imm32 R6, 0x0d3f0c0a;
+	R6.H = (A1 -= R4.L * R0.L) (M, S2RND);
+	checkreg R6, 0x7fff0c0a;
+	checkreg A1.w, 0xa7eb83d9;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x00704c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY);
+
+	dmm32 ASTAT, (0x3c50c610 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
+	dmm32 A1.w, 0xbc7ca70b;
+	dmm32 A1.x, 0xffffff80;
+	imm32 R1, 0x76b3a772;
+	imm32 R2, 0x5cc87864;
+	imm32 R5, 0x33169c34;
+	R1 = (A1 += R2.L * R5.H) (M, S2RND);
+	checkreg R1, 0x80000000;
+	checkreg A1.w, 0xd482eba3;
+	checkreg A1.x, 0xffffff80;
+	checkreg ASTAT, (0x3c50c610 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x50008480 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY);
+	dmm32 A1.w, 0xd843bd0f;
+	dmm32 A1.x, 0x00000027;
+	imm32 R0, 0xc5d36b7c;
+	imm32 R7, 0x7fff8000;
+	R0.H = (A1 += R0.L * R7.L) (M, S2RND);
+	checkreg R0, 0x7fff6b7c;
+	checkreg A1.w, 0x0e01bd0f;
+	checkreg A1.x, 0x00000028;
+	checkreg ASTAT, (0x50008480 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _V_COPY | _AN);
+	dmm32 A1.w, 0xcf30f0be;
+	dmm32 A1.x, 0xffffffad;
+	imm32 R0, 0x6d8f3470;
+	imm32 R4, 0x4174b386;
+	imm32 R6, 0x0793b3dd;
+	R0.H = (A1 -= R4.L * R6.H) (M, S2RND);
+	checkreg R0, 0x80003470;
+	checkreg A1.w, 0xd17430cc;
+	checkreg A1.x, 0xffffffad;
+	checkreg ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x60700c10 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0xc867b111;
+	dmm32 A1.x, 0xffffff90;
+	imm32 R4, 0x580f445e;
+	imm32 R5, 0x1fb2e64b;
+	imm32 R6, 0xb6bc814b;
+	R6.H = (A1 += R5.L * R4.L) (M, S2RND);
+	checkreg R6, 0x8000814b;
+	checkreg A1.w, 0xc18a2c9b;
+	checkreg A1.x, 0xffffff90;
+	checkreg ASTAT, (0x60700c10 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x4070c080 | _AV0S | _CC);
+	dmm32 A1.w, 0xe1239b9f;
+	dmm32 A1.x, 0xffffffcd;
+	imm32 R4, 0xe4d2beb4;
+	imm32 R5, 0x1c919600;
+	imm32 R6, 0x18356124;
+	R5.H = (A1 -= R4.L * R6.L) (M, S2RND);
+	checkreg R5, 0x80009600;
+	checkreg A1.w, 0xf9ea964f;
+	checkreg A1.x, 0xffffffcd;
+	checkreg ASTAT, (0x4070c080 | _VS | _V | _AV0S | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x50608210 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xe8c00d5a;
+	dmm32 A1.x, 0xffffffbe;
+	imm32 R1, 0x2baf99f2;
+	imm32 R4, 0x03e69887;
+	imm32 R7, 0x07f45a0f;
+	R1 = (A1 -= R7.L * R4.H) (M, S2RND);
+	checkreg R1, 0x80000000;
+	checkreg A1.w, 0xe760f6e0;
+	checkreg A1.x, 0xffffffbe;
+	checkreg ASTAT, (0x50608210 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0029.S b/sim/testsuite/sim/bfin/random_0029.S
new file mode 100644
index 0000000..c754995
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0029.S
@@ -0,0 +1,184 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
+	dmm32 A1.w, 0xdf7ce5c7;
+	dmm32 A1.x, 0xffffff9c;
+	imm32 R0, 0x098ecb70;
+	imm32 R1, 0x80000000;
+	R1.H = (A1 += R0.L * R1.H) (M, ISS2);
+	checkreg R1, 0x80000000;
+	checkreg A1.w, 0xc534e5c7;
+	checkreg A1.x, 0xffffff9c;
+	checkreg ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x00100600 | _VS | _AQ | _AZ);
+	dmm32 A1.w, 0xdf39474d;
+	dmm32 A1.x, 0xffffffd9;
+	imm32 R2, 0x64864b87;
+	imm32 R3, 0x61a97f85;
+	imm32 R6, 0x1bcacb1a;
+	R2.H = (A1 -= R6.L * R3.L) (M, ISS2);
+	checkreg R2, 0x80004b87;
+	checkreg A1.w, 0xf992dccb;
+	checkreg A1.x, 0xffffffd9;
+	checkreg ASTAT, (0x00100600 | _VS | _V | _AQ | _V_COPY | _AZ);
+
+	dmm32 ASTAT, (0x50f0c290 | _VS | _AC0 | _AQ | _CC | _AC0_COPY);
+	dmm32 A1.w, 0xb0a49eb4;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x1a1607f3;
+	imm32 R1, 0x6dcc7fff;
+	imm32 R6, 0x80008000;
+	R6.H = (A1 -= R1.L * R0.H) (M, ISS2);
+	checkreg R6, 0x7fff8000;
+	checkreg A1.w, 0xa399b8ca;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x50f0c290 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x48b04c10 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x91b35cde;
+	dmm32 A1.x, 0x0000006c;
+	imm32 R1, 0xf473c458;
+	imm32 R5, 0x1358b0c2;
+	imm32 R7, 0xfbf00410;
+	R5.H = (A1 -= R1.L * R7.H) (M, ISS2);
+	checkreg R5, 0x7fffb0c2;
+	checkreg A1.w, 0xcc69025e;
+	checkreg A1.x, 0x0000006c;
+	checkreg ASTAT, (0x48b04c10 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x1ca04210 | _VS | _AC0 | _AQ | _AN | _AZ);
+	dmm32 A1.w, 0xf516677c;
+	dmm32 A1.x, 0x00000015;
+	imm32 R5, 0x218d4960;
+	imm32 R6, 0xfa8c8000;
+	R5 = (A1 -= R6.L * R5.H) (M, ISS2);
+	checkreg R5, 0x7fffffff;
+	checkreg A1.w, 0x05dce77c;
+	checkreg A1.x, 0x00000016;
+	checkreg ASTAT, (0x1ca04210 | _VS | _V | _AC0 | _AQ | _V_COPY | _AN | _AZ);
+
+	dmm32 ASTAT, (0x04004490 | _VS | _AC1 | _AN);
+	dmm32 A1.w, 0xd1795d0a;
+	dmm32 A1.x, 0x00000000;
+	imm32 R2, 0x67bd270e;
+	imm32 R3, 0xda302534;
+	imm32 R7, 0x7fffa2af;
+	R2.H = (A1 += R7.L * R3.L) (M, ISS2);
+	checkreg R2, 0x7fff270e;
+	checkreg A1.w, 0xc3e9b396;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x04004490 | _VS | _V | _AC1 | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x60600490 | _VS | _AV1S | _AC1 | _CC | _AC0_COPY | _AZ);
+	dmm32 A1.w, 0xeb8abaea;
+	dmm32 A1.x, 0x00000036;
+	imm32 R1, 0x111687e8;
+	imm32 R5, 0x111687e8;
+	R1 = (A1 += R1.L * R5.L) (M, ISS2);
+	checkreg R1, 0x7fffffff;
+	checkreg A1.w, 0xabc93d2a;
+	checkreg A1.x, 0x00000036;
+	checkreg ASTAT, (0x60600490 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ);
+
+	dmm32 ASTAT, (0x30200e80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN);
+	dmm32 A1.w, 0xd3275e78;
+	dmm32 A1.x, 0xffffff89;
+	imm32 R3, 0xfee80d8d;
+	imm32 R6, 0x1c1a8000;
+	imm32 R7, 0x00000000;
+	R3 = (A1 += R7.L * R6.L) (M, ISS2);
+	checkreg R3, 0x80000000;
+	checkreg A1.w, 0xd3275e78;
+	checkreg A1.x, 0xffffff89;
+	checkreg ASTAT, (0x30200e80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x50208610 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY);
+	dmm32 A1.w, 0xb3b71810;
+	dmm32 A1.x, 0x00000000;
+	imm32 R4, 0xfc2f7ffe;
+	imm32 R5, 0x7fffffff;
+	imm32 R7, 0x3488c040;
+	R7.H = (A1 -= R4.L * R5.H) (M, ISS2);
+	checkreg R7, 0x7fffc040;
+	checkreg A1.w, 0x73b8980e;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x48d04410 | _VS | _AV1S | _AV0S | _AC0 | _AQ);
+	dmm32 A1.w, 0xeb066305;
+	dmm32 A1.x, 0xffffff9c;
+	imm32 R0, 0x80002105;
+	imm32 R4, 0xf4fbe11e;
+	imm32 R7, 0xffffb83a;
+	R7 = (A1 += R0.L * R4.L) (M, ISS2);
+	checkreg R7, 0x80000000;
+	checkreg A1.w, 0x080fa69b;
+	checkreg A1.x, 0xffffff9d;
+	checkreg ASTAT, (0x48d04410 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY);
+
+	dmm32 ASTAT, (0x3850c090 | _VS | _AV1S | _AV0S | _AC1 | _CC);
+	dmm32 A1.w, 0xdfed6537;
+	dmm32 A1.x, 0xffffffae;
+	imm32 R0, 0xe962c700;
+	imm32 R4, 0x32c97fff;
+	imm32 R7, 0x28da7373;
+	R4.H = (A1 += R7.L * R0.H) (M, ISS2);
+	checkreg R4, 0x80007fff;
+	checkreg A1.w, 0x492d423d;
+	checkreg A1.x, 0xffffffaf;
+	checkreg ASTAT, (0x3850c090 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x78a0ce00 | _VS | _AV1S | _AC0 | _AQ | _CC);
+	dmm32 A1.w, 0x8c733a78;
+	dmm32 A1.x, 0x0000002d;
+	imm32 R1, 0x3840acb0;
+	imm32 R3, 0x47b843ad;
+	imm32 R7, 0x7fff4d00;
+	R7 = (A1 += R1.L * R3.H) (M, ISS2);
+	checkreg R7, 0x7fffffff;
+	checkreg A1.w, 0x751c28f8;
+	checkreg A1.x, 0x0000002d;
+	checkreg ASTAT, (0x78a0ce00 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x3cf08880 | _VS | _AV1S | _AV0S | _AC0);
+	dmm32 A1.w, 0xbde0b55f;
+	dmm32 A1.x, 0xfffffffd;
+	imm32 R0, 0x80002300;
+	imm32 R5, 0x635db45a;
+	imm32 R7, 0x67e67af3;
+	R7 = (A1 += R0.L * R5.L) (M, ISS2);
+	checkreg R7, 0x80000000;
+	checkreg A1.w, 0xd689035f;
+	checkreg A1.x, 0xfffffffd;
+	checkreg ASTAT, (0x3cf08880 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY);
+
+	dmm32 ASTAT, (0x58608410 | _VS | _AQ | _CC | _AZ);
+	dmm32 A1.w, 0xe4660b32;
+	dmm32 A1.x, 0xffffff84;
+	imm32 R1, 0x2c6c9118;
+	imm32 R2, 0x007793ad;
+	imm32 R7, 0x526c17d9;
+	R1.H = (A1 -= R2.L * R7.L) (M, ISS2);
+	checkreg R1, 0x80009118;
+	checkreg A1.w, 0xee7d528d;
+	checkreg A1.x, 0xffffff84;
+	checkreg ASTAT, (0x58608410 | _VS | _V | _AQ | _CC | _V_COPY | _AZ);
+
+	dmm32 ASTAT, (0x2020c210 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x8da6c28f;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0x0000fff7;
+	imm32 R4, 0xf85a0000;
+	imm32 R7, 0x7fff0000;
+	R7 = (A1 += R4.L * R1.L) (M, ISS2);
+	checkreg R7, 0x7fffffff;
+	checkreg A1.w, 0x8da6c28f;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x2020c210 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0030.S b/sim/testsuite/sim/bfin/random_0030.S
new file mode 100644
index 0000000..417fb28
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0030.S
@@ -0,0 +1,177 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x00a0cc80 | _VS | _AV1S | _AQ | _CC | _AN);
+	dmm32 A1.w, 0x8f7fea28;
+	dmm32 A1.x, 0x00000005;
+	imm32 R2, 0x000014f2;
+	imm32 R4, 0x7fff7fff;
+	imm32 R7, 0x14d3a258;
+	R7.H = (A1 -= R4.L * R2.H) (M, T);
+	checkreg R7, 0x7fffa258;
+	checkreg A1.w, 0x8f7fea28;
+	checkreg A1.x, 0x00000005;
+	checkreg ASTAT, (0x00a0cc80 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
+	dmm32 A1.w, 0xbfed6ffc;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x7fffffff;
+	imm32 R5, 0x00000000;
+	imm32 R6, 0xf70a7fff;
+	R0.H = (A1 -= R5.L * R6.L) (M, T);
+	checkreg ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
+	checkreg A1.w, 0xbfed6ffc;
+	checkreg A1.x, 0x00000000;
+	checkreg R0, 0x7fffffff;
+	checkreg R5, 0x00000000;
+	checkreg R6, 0xf70a7fff;
+
+	dmm32 ASTAT, (0x2c508a10 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
+	dmm32 A1.w, 0xfffd8001;
+	dmm32 A1.x, 0x00000000;
+	imm32 R3, 0x00018000;
+	imm32 R4, 0x7fff8000;
+	imm32 R5, 0x7fff0002;
+	R3.H = (A1 += R5.L * R4.L) (M, T);
+	checkreg R3, 0x7fff8000;
+	checkreg A1.w, 0xfffe8001;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x2c508a10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY);
+
+	dmm32 ASTAT, (0x28408c90 | _VS | _AV1S | _AC0 | _AQ | _AC0_COPY | _AN);
+	dmm32 A1.w, 0x842fbc0a;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x04c44422;
+	imm32 R3, 0x40f67fff;
+	imm32 R7, 0x448c0856;
+	R7.H = (A1 -= R3.L * R0.H) (M, T);
+	checkreg R7, 0x7fff0856;
+	checkreg A1.w, 0x81cdc0ce;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x28408c90 | _VS | _V | _AV1S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x44708c10 | _AV1S | _CC | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xaa016cf5;
+	dmm32 A1.x, 0xffffffdb;
+	imm32 R2, 0x25908079;
+	imm32 R5, 0x46eabfcd;
+	imm32 R7, 0x67066230;
+	R2.H = (A1 += R5.L * R7.H) (M, T);
+	checkreg R2, 0x80008079;
+	checkreg A1.w, 0x902b66c3;
+	checkreg A1.x, 0xffffffdb;
+	checkreg ASTAT, (0x44708c10 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+	dmm32 A1.w, 0x8eef28b0;
+	dmm32 A1.x, 0x00000023;
+	imm32 R0, 0x000156b2;
+	imm32 R1, 0xfc1a8000;
+	imm32 R5, 0x7fff7fff;
+	R5.H = (A1 += R1.L * R0.H) (M, T);
+	checkreg A1.w, 0x8eeea8b0;
+	checkreg A1.x, 0x00000023;
+	checkreg ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x74208e00 | _VS | _AV0S | _AC0 | _AQ | _AC0_COPY);
+	dmm32 A1.w, 0xed3c9973;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x80000000;
+	imm32 R1, 0x7fff8000;
+	imm32 R2, 0x00000000;
+	R1.H = (A1 -= R2.L * R0.H) (M, T);
+	checkreg ASTAT, (0x74208e00 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY);
+	checkreg A1.w, 0xed3c9973;
+	checkreg A1.x, 0x00000000;
+	checkreg R0, 0x80000000;
+	checkreg R1, 0x7fff8000;
+	checkreg R2, 0x00000000;
+
+	dmm32 ASTAT, (0x10308800 | _VS | _AV0S | _AC0 | _AC0_COPY);
+	dmm32 A1.w, 0x8b345e6e;
+	dmm32 A1.x, 0x00000000;
+	imm32 R3, 0xc40c1663;
+	imm32 R4, 0xd0347fff;
+	imm32 R7, 0x4249da20;
+	R3.H = (A1 += R4.L * R7.H) (M, T);
+	checkreg R3, 0x7fff1663;
+	checkreg A1.w, 0xac589c25;
+	checkreg A1.x, 0x00000000;
+	checkreg ASTAT, (0x10308800 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY);
+
+	dmm32 ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ);
+	dmm32 A1.w, 0xa333ecbc;
+	dmm32 A1.x, 0xffffffea;
+	imm32 R2, 0x7fffffff;
+	imm32 R3, 0x72ea7fff;
+	imm32 R4, 0x07348ad1;
+	R4.H = (A1 += R2.L * R3.L) (M, T);
+	checkreg R4, 0x80008ad1;
+	checkreg A1.w, 0xa3336cbd;
+	checkreg A1.x, 0xffffffea;
+	checkreg ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ);
+
+	dmm32 ASTAT, (0x44904e00 | _VS);
+	dmm32 A1.w, 0x90202372;
+	dmm32 A1.x, 0xffffffc4;
+	imm32 R2, 0x138ac9fc;
+	imm32 R3, 0x720a427f;
+	imm32 R4, 0x800000f5;
+	R3.H = (A1 += R4.L * R2.H) (M, T);
+	checkreg R3, 0x8000427f;
+	checkreg A1.w, 0x9032d684;
+	checkreg A1.x, 0xffffffc4;
+	checkreg ASTAT, (0x44904e00 | _VS | _V | _V_COPY);
+
+	dmm32 ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
+	dmm32 A1.w, 0xe9c97364;
+	dmm32 A1.x, 0xffffffef;
+	imm32 R2, 0x001dffe9;
+	imm32 R3, 0x50f06d20;
+	imm32 R6, 0x6179b75b;
+	R6.H = (A1 -= R3.L * R2.L) (M, T);
+	checkreg R6, 0x8000b75b;
+	checkreg A1.w, 0x7cb34144;
+	checkreg A1.x, 0xffffffef;
+	checkreg ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xf3d34812;
+	dmm32 A1.x, 0xffffff95;
+	imm32 R1, 0xf7419a18;
+	imm32 R6, 0x0fdf83b3;
+	imm32 R7, 0x0b831070;
+	R7.H = (A1 -= R6.L * R1.H) (M, T);
+	checkreg R7, 0x80001070;
+	checkreg A1.w, 0x6be1229f;
+	checkreg A1.x, 0xffffff96;
+	checkreg ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
+
+	dmm32 ASTAT, (0x3060ce80 | _VS | _AV1S | _AC1 | _CC | _AN);
+	dmm32 A1.w, 0xe0c1fc60;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0x00e97fff;
+	imm32 R7, 0x3fff0001;
+	R1.H = (A1 += R1.L * R7.H) (M, T);
+	checkreg R1, 0x7fff7fff;
+	checkreg A1.w, 0x00c13c61;
+	checkreg A1.x, 0x00000001;
+	checkreg ASTAT, (0x3060ce80 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x3c80c000 | _VS | _AV0S | _AC0_COPY | _AN);
+	dmm32 A1.w, 0xb0e43973;
+	dmm32 A1.x, 0xffffffbc;
+	imm32 R0, 0x511a6fe3;
+	imm32 R1, 0x43fe2c80;
+	imm32 R2, 0x424b5c19;
+	R0.H = (A1 -= R2.L * R1.H) (M, T);
+	checkreg R0, 0x80006fe3;
+	checkreg A1.w, 0x986e4da5;
+	checkreg A1.x, 0xffffffbc;
+	checkreg ASTAT, (0x3c80c000 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0032.S b/sim/testsuite/sim/bfin/random_0032.S
new file mode 100644
index 0000000..bfded41
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0032.S
@@ -0,0 +1,154 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x74308400 | _VS | _AV1S | _AV0S | _CC | _AN);
+	dmm32 A0.w, 0x5d4cf98c;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R0, 0xba16ffff;
+	imm32 R4, 0x8000109d;
+	imm32 R6, 0x8000b212;
+	R6.L = (A0 -= R4.L * R0.L) (IH);
+	checkreg R6, 0x80008000;
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x74308400 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x34e0ce80 | _VS | _V | _AV1S | _V_COPY | _AN);
+	dmm32 A0.w, 0x64bb88af;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R5, 0x00008000;
+	imm32 R7, 0x0001ad69;
+	R5.L = (A0 += R7.H * R7.L) (IH);
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x34e0ce80 | _VS | _V | _AV1S | _AV0S | _AV0 | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x4c204c10 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN);
+	dmm32 A1.w, 0x75642aaf;
+	dmm32 A1.x, 0xffffffff;
+	imm32 R2, 0x133dffff;
+	imm32 R4, 0xc00006aa;
+	imm32 R7, 0x7fffffff;
+	R4.H = (A1 -= R2.L * R7.H) (IH);
+	checkreg R4, 0x800006aa;
+	checkreg A1.w, 0x80000000;
+	checkreg A1.x, 0xffffffff;
+	checkreg ASTAT, (0x4c204c10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x48600400 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AN);
+	dmm32 A0.w, 0x534a596c;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R1, 0x7fff86a7;
+	imm32 R5, 0x1163d244;
+	R1.L = (A0 -= R5.L * R1.L) (IH);
+	checkreg R1, 0x7fff8000;
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x48600400 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x38008c90 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
+	dmm32 A1.w, 0x80000000;
+	dmm32 A1.x, 0xffffffff;
+	imm32 R0, 0x7fffffff;
+	imm32 R1, 0xdee9214c;
+	imm32 R4, 0x79f3c80a;
+	R1.H = (A1 += R0.L * R4.H) (M, IH);
+	checkreg R1, 0x8000214c;
+	checkreg ASTAT, (0x38008c90 | _VS | _AV1S | _AV1 | _AC1 | _CC | _AN);
+
+	dmm32 ASTAT, (0x4cb00a00 | _VS | _AV1S | _AV0S | _AC1 | _AN);
+	dmm32 A0.w, 0x804e7e2f;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R1, 0x3fccdf09;
+	imm32 R2, 0x09e71015;
+	imm32 R6, 0x761ac984;
+	R2.L = (A0 += R6.L * R1.H) (IH);
+	checkreg R2, 0x09e78000;
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x4cb00a00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _V_COPY | _AN);
+
+	dmm32 ASTAT, (0x08904c00 | _VS | _AV0S | _AQ | _AZ);
+	dmm32 A0.w, 0x00000000;
+	dmm32 A0.x, 0x00000000;
+	imm32 R1, 0x80000000;
+	imm32 R2, 0x0001de54;
+	imm32 R5, 0x80000000;
+	R1.L = (A0 -= R5.H * R2.H) (TFU);
+	checkreg ASTAT, (0x08904c00 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ);
+	checkreg A0.w, 0x00000000;
+	checkreg A0.x, 0x00000000;
+	checkreg R1, 0x80000000;
+	checkreg R2, 0x0001de54;
+	checkreg R5, 0x80000000;
+
+	dmm32 ASTAT, (0x00d04810 | _VS | _AV0S | _CC | _AC0_COPY | _AZ);
+	dmm32 A0.w, 0x00000000;
+	dmm32 A0.x, 0x00000000;
+	imm32 R4, 0x00020000;
+	imm32 R5, 0x35a26677;
+	R4.L = (A0 -= R5.H * R4.H) (TFU);
+	checkreg ASTAT, (0x00d04810 | _VS | _V | _AV0S | _AV0 | _CC | _V_COPY | _AC0_COPY | _AZ);
+	checkreg A0.w, 0x00000000;
+	checkreg A0.x, 0x00000000;
+	checkreg R4, 0x00020000;
+	checkreg R5, 0x35a26677;
+
+	dmm32 ASTAT, (0x08100a80 | _VS | _AV0S | _AQ | _CC);
+	dmm32 A0.w, 0x00000000;
+	dmm32 A0.x, 0x00000000;
+	imm32 R0, 0x000300cc;
+	imm32 R4, 0x00029150;
+	imm32 R7, 0x00ff00ff;
+	R4.L = (A0 -= R0.L * R7.L) (IU);
+	checkreg R4, 0x00020000;
+	checkreg A0.w, 0x00000000;
+	checkreg A0.x, 0x00000000;
+	checkreg ASTAT, (0x08100a80 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x6c20c400 | _VS | _AV1S | _AV0S | _CC);
+	dmm32 A0.w, 0x860c9ac9;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R2, 0x860c9a1b;
+	R2.L = (A0 -= R2.H * R2.L) (IH);
+	checkreg R2, 0x860c8000;
+	checkreg A0.w, 0x80000000;
+	checkreg A0.x, 0xffffffff;
+	checkreg ASTAT, (0x6c20c400 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x20f00c10 | _VS | _AV0S | _AQ);
+	dmm32 A0.w, 0x0000de90;
+	dmm32 A0.x, 0x00000000;
+	imm32 R0, 0x00000003;
+	imm32 R1, 0xfffd8000;
+	imm32 R5, 0x4a31921c;
+	R1.L = (A0 -= R5.L * R0.L) (FU);
+	checkreg R1, 0xfffd0000;
+	checkreg A0.w, 0x00000000;
+	checkreg A0.x, 0x00000000;
+	checkreg ASTAT, (0x20f00c10 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY);
+
+	dmm32 ASTAT, (0x38700690 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY);
+	dmm32 A1.w, 0x00000000;
+	dmm32 A1.x, 0x00000000;
+	imm32 R0, 0x58863d39;
+	imm32 R1, 0x45377355;
+	imm32 R6, 0x00030000;
+	R1.H = (A1 -= R0.L * R6.H) (TFU);
+	checkreg R1, 0x00007355;
+	checkreg ASTAT, (0x38700690 | _VS | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY);
+
+	dmm32 ASTAT, (0x48704880 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
+	dmm32 A0.w, 0x7fffd68a;
+	dmm32 A0.x, 0xffffffff;
+	imm32 R7, 0x06d88000;
+	R7.L = A0 (IH);
+	checkreg A0.w, 0x7fffd68a;
+	checkreg A0.x, 0xffffffff;
+	checkreg R7, 0x06d88000;
+	checkreg ASTAT, (0x48704880 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
+
+	pass
diff --git a/sim/testsuite/sim/bfin/random_0035.S b/sim/testsuite/sim/bfin/random_0035.S
new file mode 100644
index 0000000..7c10517
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0035.S
@@ -0,0 +1,31 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+	start
+
+	dmm32 ASTAT, (0x3080ca10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY);
+	dmm32 A0.w, 0xee917987;
+	dmm32 A0.x, 0x0000007f;
+	dmm32 A1.w, 0x116e8678;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0x4d56fd82;
+	R1.L = (A0 += A1);
+	checkreg R1, 0x4d567fff;
+	checkreg A0.w, 0xffffffff;
+	checkreg A0.x, 0x0000007f;
+	checkreg ASTAT, (0x3080ca10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY);
+
+	dmm32 ASTAT, (0x00c04290 | _VS | _V | _AV0S | _V_COPY);
+	dmm32 A0.w, 0xe4f8e4c1;
+	dmm32 A0.x, 0x0000007f;
+	dmm32 A1.w, 0x1b071b3e;
+	dmm32 A1.x, 0x00000000;
+	imm32 R1, 0x4b5126c6;
+	R1.L = (A0 += A1);
+	checkreg R1, 0x4b517fff;
+	checkreg A0.w, 0xffffffff;
+	checkreg A0.x, 0x0000007f;
+	checkreg ASTAT, (0x00c04290 | _VS | _V | _AV0S | _V_COPY);
+
+	pass
author	Mike Frysinger <vapier@gentoo.org>	2011-06-18 20:27:26 +0000
committer	Mike Frysinger <vapier@gentoo.org>	2011-06-18 20:27:26 +0000
commit	4bd2c0c31ccea3032031648e7497bb7d1c04cc39 (patch)
tree	6838d746b4775522de45e3065bcf81f9fa8d2db0 /sim/testsuite
parent	a0a71a7f8b85f3d25403d140b7fb14b54b3e7f4a (diff)
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