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| author | DJ Delorie <dj@redhat.com> | 2004-09-13 21:02:33 +0000 |
|---|---|---|
| committer | DJ Delorie <dj@redhat.com> | 2004-09-13 21:02:33 +0000 |
| commit | fdd2f0d80433c7a0d9a80454a70f09c2aebdad96 (patch) | |
| tree | d3000cf1110a6e7bd325bef59d9da3f4c12960b0 /sim/testsuite | |
| parent | 2c0fc04208c99d81f19da8555adb261e557849f5 (diff) | |
| download | gdb-fdd2f0d80433c7a0d9a80454a70f09c2aebdad96.zip gdb-fdd2f0d80433c7a0d9a80454a70f09c2aebdad96.tar.gz gdb-fdd2f0d80433c7a0d9a80454a70f09c2aebdad96.tar.bz2 | |
* sim/sh/allinsn.exp: Set global_as_options and
global_ld_options appropriately for little endian builds.
* sim/sh/movua.s: Support little endian.
Diffstat (limited to 'sim/testsuite')
| -rw-r--r-- | sim/testsuite/sim/sh/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/testsuite/sim/sh/allinsn.exp | 10 | ||||
| -rw-r--r-- | sim/testsuite/sim/sh/movua.s | 68 |
3 files changed, 84 insertions, 0 deletions
diff --git a/sim/testsuite/sim/sh/ChangeLog b/sim/testsuite/sim/sh/ChangeLog index b1ad5ca..33938fe 100644 --- a/sim/testsuite/sim/sh/ChangeLog +++ b/sim/testsuite/sim/sh/ChangeLog @@ -1,3 +1,9 @@ +2004-09-13 DJ Delorie <dj@redhat.com> + + * sim/sh/allinsn.exp: Set global_as_options and + global_ld_options appropriately for little endian builds. + * sim/sh/movua.s: Support little endian. + 2004-09-08 Michael Snyder <msnyder@redhat.com> Commited by Corinna Vinschen <vinschen@redhat.com> diff --git a/sim/testsuite/sim/sh/allinsn.exp b/sim/testsuite/sim/sh/allinsn.exp index d7e9ddc..40d1392 100644 --- a/sim/testsuite/sim/sh/allinsn.exp +++ b/sim/testsuite/sim/sh/allinsn.exp @@ -2,6 +2,16 @@ set all "sh shdsp" +set global_as_options "" +set global_ld_options "" + +foreach opt $board_variant_list { + switch "x$opt" { + x-ml { set global_as_options "-little --defsym LITTLE=1" + set global_ld_options "-EL" } + } +} + if [istarget sh-*elf] { run_sim_test add.s $all run_sim_test and.s $all diff --git a/sim/testsuite/sim/sh/movua.s b/sim/testsuite/sim/sh/movua.s index e8620f0..fa12fe5 100644 --- a/sim/testsuite/sim/sh/movua.s +++ b/sim/testsuite/sim/sh/movua.s @@ -10,55 +10,107 @@ movua_1: set_grs_a5a5 mov.l srcp, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x03020100 +.else assertreg0 0x00010203 +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x04030201 +.else assertreg0 0x01020304 +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x05040302 +.else assertreg0 0x02030405 +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x06050403 +.else assertreg0 0x03040506 +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x07060504 +.else assertreg0 0x04050607 +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x08070605 +.else assertreg0 0x05060708 +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x09080706 +.else assertreg0 0x06070809 +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0a090807 +.else assertreg0 0x0708090a +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0b0a0908 +.else assertreg0 0x08090a0b +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0c0b0a09 +.else assertreg0 0x090a0b0c +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0d0c0b0a +.else assertreg0 0x0a0b0c0d +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0e0d0c0b +.else assertreg0 0x0b0c0d0e +.endif add #1, r1 movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0f0e0d0c +.else assertreg0 0x0c0d0e0f +.endif assertreg src+12, r1 test_gr_a5a5 r2 @@ -87,25 +139,41 @@ movua_4: set_grs_a5a5 mov.l srcp2, r1 movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x03020100 +.else assertreg0 0x00010203 +.endif assertreg src+4, r1 mov.l srcp2, r1 add #1, r1 movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x04030201 +.else assertreg0 0x01020304 +.endif assertreg src+5, r1 mov.l srcp2, r1 add #2, r1 movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x05040302 +.else assertreg0 0x02030405 +.endif assertreg src+6, r1 mov.l srcp2, r1 add #3, r1 movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x06050403 +.else assertreg0 0x03040506 +.endif assertreg src+7, r1 test_gr_a5a5 r2 |