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| author | Mike Frysinger <vapier@gentoo.org> | 2011-09-29 03:19:47 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-09-29 03:19:47 +0000 |
| commit | 39c1f96aef420f7b82935a370432c054d07b2476 (patch) | |
| tree | b2fd534fcf658822dce9f068725df0cbefcc72c1 /sim/testsuite | |
| parent | 24bdad53a9b175571b2681bbc4b567959f6ad344 (diff) | |
| download | gdb-39c1f96aef420f7b82935a370432c054d07b2476.zip gdb-39c1f96aef420f7b82935a370432c054d07b2476.tar.gz gdb-39c1f96aef420f7b82935a370432c054d07b2476.tar.bz2 | |
sim: bfin: use store buffer for VIT_MAX insns
The VIT_MAX insns can be used in parallel, so we need to use the store
buffer so we don't clobber the output register before we get a chance
to do a memory store with it.
Reported-by: Kai Iskratsch <kai@stella.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/testsuite')
| -rw-r--r-- | sim/testsuite/sim/bfin/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/testsuite/sim/bfin/vit_max2.s | 53 |
2 files changed, 57 insertions, 0 deletions
diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog index ec487df..72c47e0 100644 --- a/sim/testsuite/sim/bfin/ChangeLog +++ b/sim/testsuite/sim/bfin/ChangeLog @@ -1,3 +1,7 @@ +2011-09-28 Mike Frysinger <vapier@gentoo.org> + + * vit_max2.s: New tests for parallel VIT_MAX insns. + 2011-06-18 Robin Getz <robin.getz@analog.com> * random_0019.S, random_0020.S, random_0021.S, random_0022.S, diff --git a/sim/testsuite/sim/bfin/vit_max2.s b/sim/testsuite/sim/bfin/vit_max2.s new file mode 100644 index 0000000..b7c6a0e --- /dev/null +++ b/sim/testsuite/sim/bfin/vit_max2.s @@ -0,0 +1,53 @@ +# Blackfin testcase for parallel VIT_MAX (taken from PRM) +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, scratch + + # Do parallel VIT_MAX's with stores to same reg; don't really + # care what the result is of VIT_MAX as long as it doesn't + # clobber the memory store. + + imm32 R1, 0xFFFF0000 + imm32 R2, 0x0000FFFF + imm32 R0, 0xFACE + R0 = VIT_MAX (R1, R2) (ASL) || W[P0] = R0.L; + imm32 R0, 0xFACE + R4 = W[P0]; + CC = R4 == R0; + IF !CC JUMP 1f; + + imm32 R5, 0xFEEDBEEF + imm32 R4, 0xDEAF0000 + imm32 R6, 0xFACE + R6 = VIT_MAX (R5, R4) (ASR) || W[P0] = R6.L; + imm32 R6, 0xFACE + R4 = W[P0]; + CC = R4 == R6; + IF !CC JUMP 1f; + + imm32 R3, 0xFFFF0000 + imm32 R1, 0xFACE + R1.L = VIT_MAX (R3) (ASL) || W[P0] = R1.L; + imm32 R1, 0xFACE + R4 = W[P0]; + CC = R4 == R1; + IF !CC JUMP 1f; + + imm32 R2, 0x1234FADE + imm32 R5, 0xFACE + R5.L = VIT_MAX (R2) (ASR) || W[P0] = R5.L; + imm32 R5, 0xFACE + R4 = W[P0]; + CC = R4 == R5; + IF !CC JUMP 1f; + + pass +1: fail + + .data +scratch: + .dw 0xffff |