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| author | Nick Clifton <nickc@redhat.com> | 1998-02-20 19:01:58 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 1998-02-20 19:01:58 +0000 |
| commit | f83a90c41984e61c84d692f725edb72af9a5efbb (patch) | |
| tree | 515ab675fd0bbda2ffb0bb26400a9ccd42f8e631 /sim/testsuite | |
| parent | 47558b4c6489f3d8f4b09e1657a949ed0616bf4d (diff) | |
| download | gdb-f83a90c41984e61c84d692f725edb72af9a5efbb.zip gdb-f83a90c41984e61c84d692f725edb72af9a5efbb.tar.gz gdb-f83a90c41984e61c84d692f725edb72af9a5efbb.tar.bz2 | |
Last of the instruction tests.
Diffstat (limited to 'sim/testsuite')
| -rw-r--r-- | sim/testsuite/ChangeLog | 10 | ||||
| -rw-r--r-- | sim/testsuite/sim/m32r/unlock.cgs | 27 |
2 files changed, 37 insertions, 0 deletions
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index d63b1d5..f628bc3 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,13 @@ +Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com> + + * sim/m32r/addv.cgs: Test ADDV instruction. + * sim/m32r/addv3.cgs: Test ADDV3 instruction. + * sim/m32r/addx.cgs: Test ADDX instruction. + * sim/m32r/lock.cgs: Test LOCK instruction. + * sim/m32r/neg.cgs: Test NEG instruction. + * sim/m32r/not.cgs: Test NOT instruction. + * sim/m32r/unlock.cgs: Test UNLOCK instruction. + Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com> * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an diff --git a/sim/testsuite/sim/m32r/unlock.cgs b/sim/testsuite/sim/m32r/unlock.cgs new file mode 100644 index 0000000..8040c3d --- /dev/null +++ b/sim/testsuite/sim/m32r/unlock.cgs @@ -0,0 +1,27 @@ +# m32r testcase for unlock $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global unlock +unlock: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + lock r5, @r4 + + mvi_h_gr r5, 0 + unlock r5, @r4 + + test_h_gr r5, 1 + + mvi_h_gr r5, 0 + unlock r5, @r4 ; This should be a nop since the processor should be unlocked. + + test_h_gr r5, 0 + pass + +data_loc: + .word 0 |