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| author | Doug Evans <dje@google.com> | 1998-02-17 21:52:53 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 1998-02-17 21:52:53 +0000 |
| commit | 6b35d9dd8968d4309054d94badcc80cc6dde84a4 (patch) | |
| tree | 8118b4571de4f192b5d8208b0785aff7b8cd722b /sim/testsuite | |
| parent | ed063d525f9a8ad0b3672983650d33056b3e5e36 (diff) | |
| download | gdb-6b35d9dd8968d4309054d94badcc80cc6dde84a4.zip gdb-6b35d9dd8968d4309054d94badcc80cc6dde84a4.tar.gz gdb-6b35d9dd8968d4309054d94badcc80cc6dde84a4.tar.bz2 | |
m32r simulator testsuite
Diffstat (limited to 'sim/testsuite')
94 files changed, 1212 insertions, 0 deletions
diff --git a/sim/testsuite/sim/m32r/add.cgs b/sim/testsuite/sim/m32r/add.cgs new file mode 100644 index 0000000..8ed2b3a --- /dev/null +++ b/sim/testsuite/sim/m32r/add.cgs @@ -0,0 +1,16 @@ +# m32r testcase for add $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add +add: + + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + add r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/add3.cgs b/sim/testsuite/sim/m32r/add3.cgs new file mode 100644 index 0000000..d1cc848 --- /dev/null +++ b/sim/testsuite/sim/m32r/add3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for add3 $dr,$sr,#$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add3 +add3: + + mvi_h_gr r5, 1 + add3 r4, r5, 2 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/addi.cgs b/sim/testsuite/sim/m32r/addi.cgs new file mode 100644 index 0000000..1448d0d --- /dev/null +++ b/sim/testsuite/sim/m32r/addi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for addi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addi +addi: + + mvi_h_gr r5, 1 + addi r5, 2 + test_h_gr r5, 3 + + pass + diff --git a/sim/testsuite/sim/m32r/addv.cgs b/sim/testsuite/sim/m32r/addv.cgs new file mode 100644 index 0000000..6a61ccc --- /dev/null +++ b/sim/testsuite/sim/m32r/addv.cgs @@ -0,0 +1,11 @@ +# m32r testcase for addv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv +addv: + + pass diff --git a/sim/testsuite/sim/m32r/addv3.cgs b/sim/testsuite/sim/m32r/addv3.cgs new file mode 100644 index 0000000..3a6c899 --- /dev/null +++ b/sim/testsuite/sim/m32r/addv3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for addv3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv3 +addv3: + + pass diff --git a/sim/testsuite/sim/m32r/and.cgs b/sim/testsuite/sim/m32r/and.cgs new file mode 100644 index 0000000..3ec7337 --- /dev/null +++ b/sim/testsuite/sim/m32r/and.cgs @@ -0,0 +1,11 @@ +# m32r testcase for and $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and +and: + + pass diff --git a/sim/testsuite/sim/m32r/and3.cgs b/sim/testsuite/sim/m32r/and3.cgs new file mode 100644 index 0000000..c581cdd --- /dev/null +++ b/sim/testsuite/sim/m32r/and3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for and3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and3 +and3: + + pass diff --git a/sim/testsuite/sim/m32r/bc24.cgs b/sim/testsuite/sim/m32r/bc24.cgs new file mode 100644 index 0000000..6bb4333 --- /dev/null +++ b/sim/testsuite/sim/m32r/bc24.cgs @@ -0,0 +1,24 @@ +# m32r testcase for bc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc24 +bc24: + + mvi_h_condbit 0 + bc.l test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.l test1pass + fail +test1pass: + + pass + diff --git a/sim/testsuite/sim/m32r/bc8.cgs b/sim/testsuite/sim/m32r/bc8.cgs new file mode 100644 index 0000000..ceb622c --- /dev/null +++ b/sim/testsuite/sim/m32r/bc8.cgs @@ -0,0 +1,23 @@ +# m32r testcase for bc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc8 +bc8: + + mvi_h_condbit 0 + bc.s test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.s test1pass + fail +test1pass: + + pass diff --git a/sim/testsuite/sim/m32r/beq.cgs b/sim/testsuite/sim/m32r/beq.cgs new file mode 100644 index 0000000..90cf470 --- /dev/null +++ b/sim/testsuite/sim/m32r/beq.cgs @@ -0,0 +1,11 @@ +# m32r testcase for beq $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beq +beq: + + pass diff --git a/sim/testsuite/sim/m32r/beqz.cgs b/sim/testsuite/sim/m32r/beqz.cgs new file mode 100644 index 0000000..436c2fa --- /dev/null +++ b/sim/testsuite/sim/m32r/beqz.cgs @@ -0,0 +1,11 @@ +# m32r testcase for beqz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beqz +beqz: + + pass diff --git a/sim/testsuite/sim/m32r/bgez.cgs b/sim/testsuite/sim/m32r/bgez.cgs new file mode 100644 index 0000000..48f90c8 --- /dev/null +++ b/sim/testsuite/sim/m32r/bgez.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bgez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgez +bgez: + + pass diff --git a/sim/testsuite/sim/m32r/bgtz.cgs b/sim/testsuite/sim/m32r/bgtz.cgs new file mode 100644 index 0000000..fa534e4 --- /dev/null +++ b/sim/testsuite/sim/m32r/bgtz.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bgtz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgtz +bgtz: + + pass diff --git a/sim/testsuite/sim/m32r/blez.cgs b/sim/testsuite/sim/m32r/blez.cgs new file mode 100644 index 0000000..be512ce --- /dev/null +++ b/sim/testsuite/sim/m32r/blez.cgs @@ -0,0 +1,11 @@ +# m32r testcase for blez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global blez +blez: + + pass diff --git a/sim/testsuite/sim/m32r/bltz.cgs b/sim/testsuite/sim/m32r/bltz.cgs new file mode 100644 index 0000000..a379e85 --- /dev/null +++ b/sim/testsuite/sim/m32r/bltz.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bltz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bltz +bltz: + + pass diff --git a/sim/testsuite/sim/m32r/bnc24.cgs b/sim/testsuite/sim/m32r/bnc24.cgs new file mode 100644 index 0000000..2699c10 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc24.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bnc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc24 +bnc24: + + pass diff --git a/sim/testsuite/sim/m32r/bnc8.cgs b/sim/testsuite/sim/m32r/bnc8.cgs new file mode 100644 index 0000000..9ed1ab1 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc8.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bnc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc8 +bnc8: + + pass diff --git a/sim/testsuite/sim/m32r/bne.cgs b/sim/testsuite/sim/m32r/bne.cgs new file mode 100644 index 0000000..598ef54 --- /dev/null +++ b/sim/testsuite/sim/m32r/bne.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bne $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bne +bne: + + pass diff --git a/sim/testsuite/sim/m32r/bnez.cgs b/sim/testsuite/sim/m32r/bnez.cgs new file mode 100644 index 0000000..eb35889 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnez.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bnez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnez +bnez: + + pass diff --git a/sim/testsuite/sim/m32r/bra24.cgs b/sim/testsuite/sim/m32r/bra24.cgs new file mode 100644 index 0000000..3469c93 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra24.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bra $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra24 +bra24: + + pass diff --git a/sim/testsuite/sim/m32r/bra8.cgs b/sim/testsuite/sim/m32r/bra8.cgs new file mode 100644 index 0000000..918f1d4 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra8.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bra $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra8 +bra8: + + pass diff --git a/sim/testsuite/sim/m32r/cmp.cgs b/sim/testsuite/sim/m32r/cmp.cgs new file mode 100644 index 0000000..477a5b1 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmp.cgs @@ -0,0 +1,11 @@ +# m32r testcase for cmp $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmp +cmp: + + pass diff --git a/sim/testsuite/sim/m32r/cmpi.cgs b/sim/testsuite/sim/m32r/cmpi.cgs new file mode 100644 index 0000000..add2a43 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for cmpi $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + + pass diff --git a/sim/testsuite/sim/m32r/cmpu.cgs b/sim/testsuite/sim/m32r/cmpu.cgs new file mode 100644 index 0000000..d959a3b --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpu.cgs @@ -0,0 +1,11 @@ +# m32r testcase for cmpu $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpu +cmpu: + + pass diff --git a/sim/testsuite/sim/m32r/cmpui.cgs b/sim/testsuite/sim/m32r/cmpui.cgs new file mode 100644 index 0000000..760663b --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpui.cgs @@ -0,0 +1,11 @@ +# m32r testcase for cmpui $src2,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpui +cmpui: + + pass diff --git a/sim/testsuite/sim/m32r/div.cgs b/sim/testsuite/sim/m32r/div.cgs new file mode 100644 index 0000000..05fe822 --- /dev/null +++ b/sim/testsuite/sim/m32r/div.cgs @@ -0,0 +1,11 @@ +# m32r testcase for div $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global div +div: + + pass diff --git a/sim/testsuite/sim/m32r/divu.cgs b/sim/testsuite/sim/m32r/divu.cgs new file mode 100644 index 0000000..5b241dc --- /dev/null +++ b/sim/testsuite/sim/m32r/divu.cgs @@ -0,0 +1,11 @@ +# m32r testcase for divu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global divu +divu: + + pass diff --git a/sim/testsuite/sim/m32r/hello.ms b/sim/testsuite/sim/m32r/hello.ms new file mode 100644 index 0000000..0cd45bc --- /dev/null +++ b/sim/testsuite/sim/m32r/hello.ms @@ -0,0 +1,18 @@ +# output: Hello world! + + .globl _start +_start: + +; write (hello world) + ldi8 r3,#14 + ld24 r2,#hello + ldi8 r1,#1 + ldi8 r0,#5 + trap #0 +; exit (0) + ldi8 r1,#0 + ldi8 r0,#1 + trap #0 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/m32r/ld-d.cgs b/sim/testsuite/sim/m32r/ld-d.cgs new file mode 100644 index 0000000..3ff3ff6 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ld $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_d +ld_d: + + pass diff --git a/sim/testsuite/sim/m32r/ld-plus.cgs b/sim/testsuite/sim/m32r/ld-plus.cgs new file mode 100644 index 0000000..fc6dfd2 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-plus.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ld $dr,@$sr+ +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_plus +ld_plus: + + pass diff --git a/sim/testsuite/sim/m32r/ld.cgs b/sim/testsuite/sim/m32r/ld.cgs new file mode 100644 index 0000000..3471aae --- /dev/null +++ b/sim/testsuite/sim/m32r/ld.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ld $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld +ld: + + pass diff --git a/sim/testsuite/sim/m32r/ld24.cgs b/sim/testsuite/sim/m32r/ld24.cgs new file mode 100644 index 0000000..2ca8273 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld24.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ld24 $dr,#$uimm24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld24 +ld24: + + pass diff --git a/sim/testsuite/sim/m32r/ldb-d.cgs b/sim/testsuite/sim/m32r/ldb-d.cgs new file mode 100644 index 0000000..711bb10 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldb $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb_d +ldb_d: + + pass diff --git a/sim/testsuite/sim/m32r/ldb.cgs b/sim/testsuite/sim/m32r/ldb.cgs new file mode 100644 index 0000000..45245c3 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldb $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb +ldb: + + pass diff --git a/sim/testsuite/sim/m32r/ldh-d.cgs b/sim/testsuite/sim/m32r/ldh-d.cgs new file mode 100644 index 0000000..6b6c66f --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh_d +ldh_d: + + pass diff --git a/sim/testsuite/sim/m32r/ldh.cgs b/sim/testsuite/sim/m32r/ldh.cgs new file mode 100644 index 0000000..8539b37 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh +ldh: + + pass diff --git a/sim/testsuite/sim/m32r/ldi16.cgs b/sim/testsuite/sim/m32r/ldi16.cgs new file mode 100644 index 0000000..4f56827 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi16.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldi $dr,$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi16 +ldi16: + + pass diff --git a/sim/testsuite/sim/m32r/ldi8.cgs b/sim/testsuite/sim/m32r/ldi8.cgs new file mode 100644 index 0000000..11d9566 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi8.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi8 +ldi8: + + pass diff --git a/sim/testsuite/sim/m32r/ldub-d.cgs b/sim/testsuite/sim/m32r/ldub-d.cgs new file mode 100644 index 0000000..e3fc03d --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldub $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub_d +ldub_d: + + pass diff --git a/sim/testsuite/sim/m32r/ldub.cgs b/sim/testsuite/sim/m32r/ldub.cgs new file mode 100644 index 0000000..649c311 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldub $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub +ldub: + + pass diff --git a/sim/testsuite/sim/m32r/lduh-d.cgs b/sim/testsuite/sim/m32r/lduh-d.cgs new file mode 100644 index 0000000..57f8e50 --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for lduh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh_d +lduh_d: + + pass diff --git a/sim/testsuite/sim/m32r/lduh.cgs b/sim/testsuite/sim/m32r/lduh.cgs new file mode 100644 index 0000000..94061d7 --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh.cgs @@ -0,0 +1,11 @@ +# m32r testcase for lduh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh +lduh: + + pass diff --git a/sim/testsuite/sim/m32r/lock.cgs b/sim/testsuite/sim/m32r/lock.cgs new file mode 100644 index 0000000..75ef76b --- /dev/null +++ b/sim/testsuite/sim/m32r/lock.cgs @@ -0,0 +1,11 @@ +# m32r testcase for lock $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lock +lock: + + pass diff --git a/sim/testsuite/sim/m32r/machi.cgs b/sim/testsuite/sim/m32r/machi.cgs new file mode 100644 index 0000000..2e2ef00 --- /dev/null +++ b/sim/testsuite/sim/m32r/machi.cgs @@ -0,0 +1,17 @@ +# m32r testcase for machi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global machi +machi: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + machi r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/maclo.cgs b/sim/testsuite/sim/m32r/maclo.cgs new file mode 100644 index 0000000..5d03539 --- /dev/null +++ b/sim/testsuite/sim/m32r/maclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for maclo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global maclo +maclo: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x1230001 + mvi_h_gr r5, 0x4560002 + maclo r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/macwhi.cgs b/sim/testsuite/sim/m32r/macwhi.cgs new file mode 100644 index 0000000..76a596d --- /dev/null +++ b/sim/testsuite/sim/m32r/macwhi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for macwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwhi +macwhi: + + pass diff --git a/sim/testsuite/sim/m32r/macwlo.cgs b/sim/testsuite/sim/m32r/macwlo.cgs new file mode 100644 index 0000000..f1092a5 --- /dev/null +++ b/sim/testsuite/sim/m32r/macwlo.cgs @@ -0,0 +1,11 @@ +# m32r testcase for macwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwlo +macwlo: + + pass diff --git a/sim/testsuite/sim/m32r/mul.cgs b/sim/testsuite/sim/m32r/mul.cgs new file mode 100644 index 0000000..7e0ccc0 --- /dev/null +++ b/sim/testsuite/sim/m32r/mul.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mul $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mul +mul: + + pass diff --git a/sim/testsuite/sim/m32r/mulhi.cgs b/sim/testsuite/sim/m32r/mulhi.cgs new file mode 100644 index 0000000..77c103d --- /dev/null +++ b/sim/testsuite/sim/m32r/mulhi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mulhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulhi +mulhi: + + mvi_h_gr r4, 0x40000 + mvi_h_gr r5, 0x50000 + mulhi r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mullo.cgs b/sim/testsuite/sim/m32r/mullo.cgs new file mode 100644 index 0000000..11aadff --- /dev/null +++ b/sim/testsuite/sim/m32r/mullo.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mullo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mullo +mullo: + + mvi_h_gr r4, 4 + mvi_h_gr r5, 5 + mullo r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mulwhi.cgs b/sim/testsuite/sim/m32r/mulwhi.cgs new file mode 100644 index 0000000..766afca --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwhi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mulwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwhi +mulwhi: + + pass diff --git a/sim/testsuite/sim/m32r/mulwlo.cgs b/sim/testsuite/sim/m32r/mulwlo.cgs new file mode 100644 index 0000000..6bd267d --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwlo.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mulwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwlo +mulwlo: + + pass diff --git a/sim/testsuite/sim/m32r/mv.cgs b/sim/testsuite/sim/m32r/mv.cgs new file mode 100644 index 0000000..b14cbe3 --- /dev/null +++ b/sim/testsuite/sim/m32r/mv.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mv +mv: + + pass diff --git a/sim/testsuite/sim/m32r/mvfachi.cgs b/sim/testsuite/sim/m32r/mvfachi.cgs new file mode 100644 index 0000000..380e37b --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfachi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvfachi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfachi +mvfachi: + + pass diff --git a/sim/testsuite/sim/m32r/mvfaclo.cgs b/sim/testsuite/sim/m32r/mvfaclo.cgs new file mode 100644 index 0000000..0e05cf0 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfaclo.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvfaclo $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfaclo +mvfaclo: + + pass diff --git a/sim/testsuite/sim/m32r/mvfacmi.cgs b/sim/testsuite/sim/m32r/mvfacmi.cgs new file mode 100644 index 0000000..580bcae --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfacmi.cgs @@ -0,0 +1,15 @@ +# m32r testcase for mvfacmi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfacmi +mvfacmi: + + mvi_h_accum0 0x12345678, 0x87654321 + mvfacmi r4 + test_h_gr r4, 0x56788765 + + pass diff --git a/sim/testsuite/sim/m32r/mvtachi.cgs b/sim/testsuite/sim/m32r/mvtachi.cgs new file mode 100644 index 0000000..827dc10 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtachi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvtachi $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtachi +mvtachi: + + pass diff --git a/sim/testsuite/sim/m32r/mvtaclo.cgs b/sim/testsuite/sim/m32r/mvtaclo.cgs new file mode 100644 index 0000000..5f628f3 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtaclo.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvtaclo $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtaclo +mvtaclo: + + pass diff --git a/sim/testsuite/sim/m32r/mvtc.cgs b/sim/testsuite/sim/m32r/mvtc.cgs new file mode 100644 index 0000000..9d824c9 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtc.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvtc $sr,$dcr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtc +mvtc: + + pass diff --git a/sim/testsuite/sim/m32r/neg.cgs b/sim/testsuite/sim/m32r/neg.cgs new file mode 100644 index 0000000..52bb44c --- /dev/null +++ b/sim/testsuite/sim/m32r/neg.cgs @@ -0,0 +1,11 @@ +# m32r testcase for neg $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global neg +neg: + + pass diff --git a/sim/testsuite/sim/m32r/nop.cgs b/sim/testsuite/sim/m32r/nop.cgs new file mode 100644 index 0000000..517d34d --- /dev/null +++ b/sim/testsuite/sim/m32r/nop.cgs @@ -0,0 +1,11 @@ +# m32r testcase for nop +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global nop +nop: + + pass diff --git a/sim/testsuite/sim/m32r/not.cgs b/sim/testsuite/sim/m32r/not.cgs new file mode 100644 index 0000000..358dac5 --- /dev/null +++ b/sim/testsuite/sim/m32r/not.cgs @@ -0,0 +1,11 @@ +# m32r testcase for not $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global not +not: + + pass diff --git a/sim/testsuite/sim/m32r/or.cgs b/sim/testsuite/sim/m32r/or.cgs new file mode 100644 index 0000000..afa629b --- /dev/null +++ b/sim/testsuite/sim/m32r/or.cgs @@ -0,0 +1,11 @@ +# m32r testcase for or $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or +or: + + pass diff --git a/sim/testsuite/sim/m32r/or3.cgs b/sim/testsuite/sim/m32r/or3.cgs new file mode 100644 index 0000000..200907a --- /dev/null +++ b/sim/testsuite/sim/m32r/or3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for or3 $dr,$sr,#$ulo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or3 +or3: + + pass diff --git a/sim/testsuite/sim/m32r/rac-d.cgs b/sim/testsuite/sim/m32r/rac-d.cgs new file mode 100644 index 0000000..201fd79 --- /dev/null +++ b/sim/testsuite/sim/m32r/rac-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rac $accd +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac_d +rac_d: + + pass diff --git a/sim/testsuite/sim/m32r/rac-ds.cgs b/sim/testsuite/sim/m32r/rac-ds.cgs new file mode 100644 index 0000000..44dc4fa --- /dev/null +++ b/sim/testsuite/sim/m32r/rac-ds.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rac $accd,$accs +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac_ds +rac_ds: + + pass diff --git a/sim/testsuite/sim/m32r/rac.cgs b/sim/testsuite/sim/m32r/rac.cgs new file mode 100644 index 0000000..35b9ae3 --- /dev/null +++ b/sim/testsuite/sim/m32r/rac.cgs @@ -0,0 +1,23 @@ +# m32r testcase for rac +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac +rac: + + mvi_h_accum0 1, 0x4001 + rac + test_h_accum0 2, 0x10000 + + mvi_h_accum0 0x3fff, 0xffff4000 + rac + test_h_accum0 0x7fff, 0xffff0000 + + mvi_h_accum0 0xffff8000, 0 + rac + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/sim/m32r/rach-d.cgs b/sim/testsuite/sim/m32r/rach-d.cgs new file mode 100644 index 0000000..52a336a --- /dev/null +++ b/sim/testsuite/sim/m32r/rach-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rach $accd +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach_d +rach_d: + + pass diff --git a/sim/testsuite/sim/m32r/rach-ds.cgs b/sim/testsuite/sim/m32r/rach-ds.cgs new file mode 100644 index 0000000..c95ccf5 --- /dev/null +++ b/sim/testsuite/sim/m32r/rach-ds.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rach $accd,$accs +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach_ds +rach_ds: + + pass diff --git a/sim/testsuite/sim/m32r/rach.cgs b/sim/testsuite/sim/m32r/rach.cgs new file mode 100644 index 0000000..efc36d8 --- /dev/null +++ b/sim/testsuite/sim/m32r/rach.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rach +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach +rach: + + pass diff --git a/sim/testsuite/sim/m32r/rem.cgs b/sim/testsuite/sim/m32r/rem.cgs new file mode 100644 index 0000000..f9416c8 --- /dev/null +++ b/sim/testsuite/sim/m32r/rem.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rem $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rem +rem: + + pass diff --git a/sim/testsuite/sim/m32r/seth.cgs b/sim/testsuite/sim/m32r/seth.cgs new file mode 100644 index 0000000..bfe57c0 --- /dev/null +++ b/sim/testsuite/sim/m32r/seth.cgs @@ -0,0 +1,11 @@ +# m32r testcase for seth $dr,#$hi16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global seth +seth: + + pass diff --git a/sim/testsuite/sim/m32r/sll.cgs b/sim/testsuite/sim/m32r/sll.cgs new file mode 100644 index 0000000..492032a --- /dev/null +++ b/sim/testsuite/sim/m32r/sll.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sll $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll +sll: + + pass diff --git a/sim/testsuite/sim/m32r/sll3.cgs b/sim/testsuite/sim/m32r/sll3.cgs new file mode 100644 index 0000000..6d2747c --- /dev/null +++ b/sim/testsuite/sim/m32r/sll3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sll3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll3 +sll3: + + pass diff --git a/sim/testsuite/sim/m32r/slli.cgs b/sim/testsuite/sim/m32r/slli.cgs new file mode 100644 index 0000000..600d27a --- /dev/null +++ b/sim/testsuite/sim/m32r/slli.cgs @@ -0,0 +1,11 @@ +# m32r testcase for slli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global slli +slli: + + pass diff --git a/sim/testsuite/sim/m32r/sra.cgs b/sim/testsuite/sim/m32r/sra.cgs new file mode 100644 index 0000000..3c72199 --- /dev/null +++ b/sim/testsuite/sim/m32r/sra.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sra $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra +sra: + + pass diff --git a/sim/testsuite/sim/m32r/sra3.cgs b/sim/testsuite/sim/m32r/sra3.cgs new file mode 100644 index 0000000..837258d --- /dev/null +++ b/sim/testsuite/sim/m32r/sra3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sra3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra3 +sra3: + + pass diff --git a/sim/testsuite/sim/m32r/srai.cgs b/sim/testsuite/sim/m32r/srai.cgs new file mode 100644 index 0000000..603c5b7 --- /dev/null +++ b/sim/testsuite/sim/m32r/srai.cgs @@ -0,0 +1,11 @@ +# m32r testcase for srai $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srai +srai: + + pass diff --git a/sim/testsuite/sim/m32r/srl.cgs b/sim/testsuite/sim/m32r/srl.cgs new file mode 100644 index 0000000..ccbf460 --- /dev/null +++ b/sim/testsuite/sim/m32r/srl.cgs @@ -0,0 +1,11 @@ +# m32r testcase for srl $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl +srl: + + pass diff --git a/sim/testsuite/sim/m32r/srl3.cgs b/sim/testsuite/sim/m32r/srl3.cgs new file mode 100644 index 0000000..d26f571 --- /dev/null +++ b/sim/testsuite/sim/m32r/srl3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for srl3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl3 +srl3: + + pass diff --git a/sim/testsuite/sim/m32r/srli.cgs b/sim/testsuite/sim/m32r/srli.cgs new file mode 100644 index 0000000..5ce6d07 --- /dev/null +++ b/sim/testsuite/sim/m32r/srli.cgs @@ -0,0 +1,11 @@ +# m32r testcase for srli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srli +srli: + + pass diff --git a/sim/testsuite/sim/m32r/st-d.cgs b/sim/testsuite/sim/m32r/st-d.cgs new file mode 100644 index 0000000..29e1066 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for st $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_d +st_d: + + pass diff --git a/sim/testsuite/sim/m32r/st-minus.cgs b/sim/testsuite/sim/m32r/st-minus.cgs new file mode 100644 index 0000000..1aed708 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-minus.cgs @@ -0,0 +1,11 @@ +# m32r testcase for st $src1,@-$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_minus +st_minus: + + pass diff --git a/sim/testsuite/sim/m32r/st-plus.cgs b/sim/testsuite/sim/m32r/st-plus.cgs new file mode 100644 index 0000000..00539d7 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-plus.cgs @@ -0,0 +1,11 @@ +# m32r testcase for st $src1,@+$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_plus +st_plus: + + pass diff --git a/sim/testsuite/sim/m32r/st.cgs b/sim/testsuite/sim/m32r/st.cgs new file mode 100644 index 0000000..cd2d9c5 --- /dev/null +++ b/sim/testsuite/sim/m32r/st.cgs @@ -0,0 +1,11 @@ +# m32r testcase for st $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st +st: + + pass diff --git a/sim/testsuite/sim/m32r/stb-d.cgs b/sim/testsuite/sim/m32r/stb-d.cgs new file mode 100644 index 0000000..533ccf0 --- /dev/null +++ b/sim/testsuite/sim/m32r/stb-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for stb $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb_d +stb_d: + + pass diff --git a/sim/testsuite/sim/m32r/stb.cgs b/sim/testsuite/sim/m32r/stb.cgs new file mode 100644 index 0000000..2b5dff1 --- /dev/null +++ b/sim/testsuite/sim/m32r/stb.cgs @@ -0,0 +1,11 @@ +# m32r testcase for stb $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb +stb: + + pass diff --git a/sim/testsuite/sim/m32r/sth-d.cgs b/sim/testsuite/sim/m32r/sth-d.cgs new file mode 100644 index 0000000..14a4711 --- /dev/null +++ b/sim/testsuite/sim/m32r/sth-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sth $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth_d +sth_d: + + pass diff --git a/sim/testsuite/sim/m32r/sth.cgs b/sim/testsuite/sim/m32r/sth.cgs new file mode 100644 index 0000000..d0dd43d --- /dev/null +++ b/sim/testsuite/sim/m32r/sth.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sth $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth +sth: + + pass diff --git a/sim/testsuite/sim/m32r/sub.cgs b/sim/testsuite/sim/m32r/sub.cgs new file mode 100644 index 0000000..8dbe6b8 --- /dev/null +++ b/sim/testsuite/sim/m32r/sub.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sub $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sub +sub: + + pass diff --git a/sim/testsuite/sim/m32r/subv.cgs b/sim/testsuite/sim/m32r/subv.cgs new file mode 100644 index 0000000..4a46fb5 --- /dev/null +++ b/sim/testsuite/sim/m32r/subv.cgs @@ -0,0 +1,11 @@ +# m32r testcase for subv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subv +subv: + + pass diff --git a/sim/testsuite/sim/m32r/subx.cgs b/sim/testsuite/sim/m32r/subx.cgs new file mode 100644 index 0000000..597373a --- /dev/null +++ b/sim/testsuite/sim/m32r/subx.cgs @@ -0,0 +1,11 @@ +# m32r testcase for subx $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subx +subx: + + pass diff --git a/sim/testsuite/sim/m32r/testutils.inc b/sim/testsuite/sim/m32r/testutils.inc new file mode 100644 index 0000000..24d925e --- /dev/null +++ b/sim/testsuite/sim/m32r/testutils.inc @@ -0,0 +1,105 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + .endm + + .macro exit rc + ldi8 r1, \rc + ldi8 r0, #1 + trap #0 + .endm + + .macro pass + ldi8 r3, 5 + ld24 r2, passmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 0 + .endm + + .macro fail + ldi8 r3, 5 + ld24 r2, failmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 1 + .endm + + .macro mvi_h_gr reg, val + .if (\val >= -128) && (\val <= 127) + ldi8 \reg, \val + .else + seth \reg, high(\val) + or3 \reg, \reg, low(\val) + .endif + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + mvi_h_gr r0, \val + beq \reg, r0, test_gr\@ + fail +test_gr\@: + .endm + + .macro mvi_h_condbit val + ldi8 r0, 0 + ldi8 r1, 1 + .if \val + cmp r0, r1 + .else + cmp r1, r0 + .endif + .endm + + .macro test_h_condbit val + .if \val + bc test_c1\@ + fail +test_c1\@: + .else + bnc test_c0\@ + fail +test_c0\@: + .endif + .endm + + .macro mvi_h_accum0 hi, lo + mvi_h_gr r0, \hi + mvtachi r0 + mvi_h_gr r0, \lo + mvtaclo r0 + .endm + + .macro test_h_accum0 hi, lo + mvfachi r1 + test_h_gr r1, \hi + mvfaclo r1 + test_h_gr r1, \lo + .endm + +# start-sanitize-m32rx + .macro mvi_h_accum1 hi, lo + mvi_h_gr r0, \hi + mvtachi r0, a1 + mvi_h_gr r0, \lo + mvtaclo r0, a1 + .endm + + .macro test_h_accum1 hi, lo + mvfachi r1, a1 + test_h_gr r1, \hi + mvfaclo r1, a1 + test_h_gr r1, \lo + .endm +# end-sanitize-m32rx diff --git a/sim/testsuite/sim/m32r/xor3.cgs b/sim/testsuite/sim/m32r/xor3.cgs new file mode 100644 index 0000000..7e1879e --- /dev/null +++ b/sim/testsuite/sim/m32r/xor3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for xor3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor3 +xor3: + + pass |