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authorM R Swami Reddy <MR.Swami.Reddy@nsc.com>2008-05-05 10:25:20 +0000
committerM R Swami Reddy <MR.Swami.Reddy@nsc.com>2008-05-05 10:25:20 +0000
commite8db345894127db4220b2b97275034e71bcbac37 (patch)
tree00733816c0cc7a5c0d81cb565d60aa5cdd32e187 /sim/testsuite
parent9c301be69b23377a65580634dcf4db00af3e40ad (diff)
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Added 3 miscellaneous testcases like read32.ms uread16.ms hw-trap.ms.
Diffstat (limited to 'sim/testsuite')
-rw-r--r--sim/testsuite/sim/cr16/hw-trap.ms10
-rw-r--r--sim/testsuite/sim/cr16/uread16.ms17
-rw-r--r--sim/testsuite/sim/cr16/uread32.ms17
3 files changed, 44 insertions, 0 deletions
diff --git a/sim/testsuite/sim/cr16/hw-trap.ms b/sim/testsuite/sim/cr16/hw-trap.ms
new file mode 100644
index 0000000..8c8c185
--- /dev/null
+++ b/sim/testsuite/sim/cr16/hw-trap.ms
@@ -0,0 +1,10 @@
+# mach(): cr16
+
+ .include "testutils.inc"
+
+ start
+
+# perform trap
+ movw $0,r2
+ movw $0x410,r0
+ pass # the pass macro use the trap 8
diff --git a/sim/testsuite/sim/cr16/uread16.ms b/sim/testsuite/sim/cr16/uread16.ms
new file mode 100644
index 0000000..54253b4
--- /dev/null
+++ b/sim/testsuite/sim/cr16/uread16.ms
@@ -0,0 +1,17 @@
+# mach: cr16
+
+ .include "testutils.inc"
+
+ start
+
+ .global read16
+read16:
+ loadw foo,r1
+ cmpw $42, r1
+ beq ok
+ fail
+ok:
+ pass
+
+foo:
+ .word 42
diff --git a/sim/testsuite/sim/cr16/uread32.ms b/sim/testsuite/sim/cr16/uread32.ms
new file mode 100644
index 0000000..c2181e5
--- /dev/null
+++ b/sim/testsuite/sim/cr16/uread32.ms
@@ -0,0 +1,17 @@
+# mach: cr16
+
+ .include "testutils.inc"
+
+ start
+
+ .global read32
+read32:
+ loadd foo, (r1,r0)
+ cmpd $0x12345678, (r1,r0)
+ beq ok
+ fail
+ok:
+ pass
+
+foo:
+ .long 0x12345678