aboutsummaryrefslogtreecommitdiff
path: root/sim/testsuite
diff options
context:
space:
mode:
authorDave Brolley <brolley@redhat.com>1998-12-17 22:25:05 +0000
committerDave Brolley <brolley@redhat.com>1998-12-17 22:25:05 +0000
commitde6fb7e7755ffdc165664bdff555645424da644a (patch)
tree4f8bf542c44d554baa7afd718d8ad934498f77a8 /sim/testsuite
parentf7fb02ba10bb945f4ac8b0192bf5ce440570e598 (diff)
downloadgdb-de6fb7e7755ffdc165664bdff555645424da644a.zip
gdb-de6fb7e7755ffdc165664bdff555645424da644a.tar.gz
gdb-de6fb7e7755ffdc165664bdff555645424da644a.tar.bz2
Thu Dec 17 17:18:43 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros. * sim/fr30/ret.cgs: Add tests fir ret:d. * sim/fr30/inte.cgs: New testcase. * sim/fr30/reti.cgs: New testcase. * sim/fr30/bra.cgs: New testcase. * sim/fr30/bno.cgs: New testcase. * sim/fr30/beq.cgs: New testcase. * sim/fr30/bne.cgs: New testcase. * sim/fr30/bc.cgs: New testcase. * sim/fr30/bnc.cgs: New testcase. * sim/fr30/bn.cgs: New testcase. * sim/fr30/bp.cgs: New testcase. * sim/fr30/bv.cgs: New testcase. * sim/fr30/bnv.cgs: New testcase. * sim/fr30/blt.cgs: New testcase. * sim/fr30/bge.cgs: New testcase. * sim/fr30/ble.cgs: New testcase. * sim/fr30/bgt.cgs: New testcase. * sim/fr30/bls.cgs: New testcase. * sim/fr30/bhi.cgs: New testcase.
Diffstat (limited to 'sim/testsuite')
-rw-r--r--sim/testsuite/sim/fr30/bc.cgs109
-rw-r--r--sim/testsuite/sim/fr30/beq.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bge.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bgt.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bhi.cgs109
-rw-r--r--sim/testsuite/sim/fr30/ble.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bls.cgs109
-rw-r--r--sim/testsuite/sim/fr30/blt.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bn.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bnc.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bne.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bno.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bnv.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bp.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bra.cgs109
-rw-r--r--sim/testsuite/sim/fr30/bv.cgs109
-rw-r--r--sim/testsuite/sim/fr30/inte.cgs36
-rw-r--r--sim/testsuite/sim/fr30/reti.cgs57
18 files changed, 1837 insertions, 0 deletions
diff --git a/sim/testsuite/sim/fr30/bc.cgs b/sim/testsuite/sim/fr30/bc.cgs
new file mode 100644
index 0000000..0502625
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bc.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bc $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bc
+bc:
+ ; Test bc $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch bc
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch bc
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch bc
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch bc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch bc
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch bc
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch bc
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch bc
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch bc
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch bc
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch bc
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch bc
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch bc
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch bc
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch bc
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch bc
+
+ ; Test bc:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch_d bc:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch_d bc:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch_d bc:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch_d bc:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch_d bc:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch_d bc:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch_d bc:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch_d bc:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch_d bc:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch_d bc:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch_d bc:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch_d bc:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch_d bc:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch_d bc:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch_d bc:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch_d bc:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/beq.cgs b/sim/testsuite/sim/fr30/beq.cgs
new file mode 100644
index 0000000..edd797e
--- /dev/null
+++ b/sim/testsuite/sim/fr30/beq.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for beq $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global beq
+beq:
+ ; Test beq $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch beq
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch beq
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch beq
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch beq
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch beq
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch beq
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch beq
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch beq
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch beq
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch beq
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch beq
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch beq
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch beq
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch beq
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch beq
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch beq
+
+ ; Test beq:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch_d beq:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch_d beq:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch_d beq:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch_d beq:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch_d beq:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch_d beq:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch_d beq:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch_d beq:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch_d beq:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch_d beq:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch_d beq:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch_d beq:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch_d beq:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch_d beq:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch_d beq:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch_d beq:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bge.cgs b/sim/testsuite/sim/fr30/bge.cgs
new file mode 100644
index 0000000..dd7796c
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bge.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bge $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bge
+bge:
+ ; Test bge $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch bge
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch bge
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch bge
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch bge
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch bge
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch bge
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch bge
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch bge
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch bge
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch bge
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch bge
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch bge
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch bge
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch bge
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch bge
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch bge
+
+ ; Test bge:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch_d bge:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch_d bge:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch_d bge:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch_d bge:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch_d bge:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch_d bge:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch_d bge:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch_d bge:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch_d bge:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch_d bge:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch_d bge:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch_d bge:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch_d bge:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch_d bge:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch_d bge:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch_d bge:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bgt.cgs b/sim/testsuite/sim/fr30/bgt.cgs
new file mode 100644
index 0000000..525ac2e
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bgt.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bgt $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bgt
+bgt:
+ ; Test bgt $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch bgt
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch bgt
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch bgt
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch bgt
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch bgt
+
+ ; Test bgt:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch_d bgt:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch_d bgt:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch_d bgt:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch_d bgt:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch_d bgt:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch_d bgt:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch_d bgt:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch_d bgt:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch_d bgt:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch_d bgt:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch_d bgt:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch_d bgt:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch_d bgt:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch_d bgt:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch_d bgt:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch_d bgt:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bhi.cgs b/sim/testsuite/sim/fr30/bhi.cgs
new file mode 100644
index 0000000..f5a1549
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bhi.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bhi $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bhi
+bhi:
+ ; Test bhi $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch bhi
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch bhi
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch bhi
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch bhi
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch bhi
+
+ ; Test bhi:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch_d bhi:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch_d bhi:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch_d bhi:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch_d bhi:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch_d bhi:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch_d bhi:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch_d bhi:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch_d bhi:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch_d bhi:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch_d bhi:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch_d bhi:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch_d bhi:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch_d bhi:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch_d bhi:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch_d bhi:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch_d bhi:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/ble.cgs b/sim/testsuite/sim/fr30/ble.cgs
new file mode 100644
index 0000000..1a33f78
--- /dev/null
+++ b/sim/testsuite/sim/fr30/ble.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for ble $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global ble
+ble:
+ ; Test ble $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch ble
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch ble
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch ble
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch ble
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch ble
+
+ ; Test ble:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch_d ble:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch_d ble:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch_d ble:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch_d ble:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch_d ble:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch_d ble:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch_d ble:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch_d ble:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch_d ble:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch_d ble:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch_d ble:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch_d ble:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch_d ble:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch_d ble:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch_d ble:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch_d ble:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bls.cgs b/sim/testsuite/sim/fr30/bls.cgs
new file mode 100644
index 0000000..c0148b7
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bls.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bls $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bls
+bls:
+ ; Test bls $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch bls
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch bls
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch bls
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch bls
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch bls
+
+ ; Test bls:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch_d bls:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch_d bls:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch_d bls:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch_d bls:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch_d bls:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch_d bls:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch_d bls:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch_d bls:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch_d bls:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch_d bls:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch_d bls:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch_d bls:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch_d bls:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch_d bls:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch_d bls:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch_d bls:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/blt.cgs b/sim/testsuite/sim/fr30/blt.cgs
new file mode 100644
index 0000000..f7b6ff1
--- /dev/null
+++ b/sim/testsuite/sim/fr30/blt.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for blt $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global blt
+blt:
+ ; Test blt $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch blt
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch blt
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch blt
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch blt
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch blt
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch blt
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch blt
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch blt
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch blt
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch blt
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch blt
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch blt
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch blt
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch blt
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch blt
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch blt
+
+ ; Test blt:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch_d blt:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch_d blt:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch_d blt:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch_d blt:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch_d blt:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch_d blt:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch_d blt:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch_d blt:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch_d blt:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch_d blt:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch_d blt:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch_d blt:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch_d blt:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch_d blt:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch_d blt:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch_d blt:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bn.cgs b/sim/testsuite/sim/fr30/bn.cgs
new file mode 100644
index 0000000..45858fc
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bn.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bn $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bn
+bn:
+ ; Test bn $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch bn
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch bn
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch bn
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch bn
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch bn
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch bn
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch bn
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch bn
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch bn
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch bn
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch bn
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch bn
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch bn
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch bn
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch bn
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch bn
+
+ ; Test bn:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch_d bn:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch_d bn:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch_d bn:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch_d bn:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch_d bn:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch_d bn:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch_d bn:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch_d bn:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch_d bn:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch_d bn:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch_d bn:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch_d bn:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch_d bn:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch_d bn:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch_d bn:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch_d bn:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bnc.cgs b/sim/testsuite/sim/fr30/bnc.cgs
new file mode 100644
index 0000000..9968c43
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bnc.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bnc $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bnc
+bc:
+ ; Test bnc $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch bnc
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch bnc
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch bnc
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch bnc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch bnc
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch bnc
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch bnc
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch bnc
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch bnc
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch bnc
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch bnc
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch bnc
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch bnc
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch bnc
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch bnc
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch bnc
+
+ ; Test bnc:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch_d bnc:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch_d bnc:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch_d bnc:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch_d bnc:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch_d bnc:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch_d bnc:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch_d bnc:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch_d bnc:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch_d bnc:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch_d bnc:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch_d bnc:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch_d bnc:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch_d bnc:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch_d bnc:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch_d bnc:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch_d bnc:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bne.cgs b/sim/testsuite/sim/fr30/bne.cgs
new file mode 100644
index 0000000..58971de
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bne.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bne $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bne
+bne:
+ ; Test bne $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch bne
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch bne
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch bne
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch bne
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch bne
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch bne
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch bne
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch bne
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch bne
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch bne
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch bne
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch bne
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch bne
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch bne
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch bne
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch bne
+
+ ; Test bne:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch_d bne:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch_d bne:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch_d bne:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch_d bne:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch_d bne:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch_d bne:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch_d bne:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch_d bne:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch_d bne:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch_d bne:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch_d bne:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch_d bne:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch_d bne:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch_d bne:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch_d bne:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch_d bne:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bno.cgs b/sim/testsuite/sim/fr30/bno.cgs
new file mode 100644
index 0000000..faef9ba
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bno.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bno $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bno
+bno:
+ ; Test bno $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch bno
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch bno
+
+ ; Test bno:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch_d bno:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch_d bno:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch_d bno:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch_d bno:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch_d bno:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch_d bno:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch_d bno:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch_d bno:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch_d bno:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch_d bno:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch_d bno:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch_d bno:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch_d bno:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch_d bno:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch_d bno:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch_d bno:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bnv.cgs b/sim/testsuite/sim/fr30/bnv.cgs
new file mode 100644
index 0000000..7615abd
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bnv.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bnv $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bnv
+bnv:
+ ; Test bnv $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch bnv
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch bnv
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch bnv
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch bnv
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch bnv
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch bnv
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch bnv
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch bnv
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch bnv
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch bnv
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch bnv
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch bnv
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch bnv
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch bnv
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch bnv
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch bnv
+
+ ; Test bnv:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch_d bnv:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch_d bnv:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch_d bnv:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch_d bnv:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch_d bnv:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch_d bnv:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch_d bnv:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch_d bnv:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ no_branch_d bnv:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ no_branch_d bnv:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch_d bnv:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch_d bnv:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ no_branch_d bnv:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ no_branch_d bnv:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch_d bnv:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch_d bnv:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bp.cgs b/sim/testsuite/sim/fr30/bp.cgs
new file mode 100644
index 0000000..3753283
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bp.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bp $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bp
+bp:
+ ; Test bp $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch bp
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch bp
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch bp
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch bp
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch bp
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch bp
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch bp
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch bp
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch bp
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch bp
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch bp
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch bp
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch bp
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch bp
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch bp
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch bp
+
+ ; Test bp:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ no_branch_d bp:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ no_branch_d bp:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch_d bp:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch_d bp:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ no_branch_d bp:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ no_branch_d bp:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch_d bp:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch_d bp:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch_d bp:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch_d bp:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch_d bp:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch_d bp:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch_d bp:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch_d bp:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch_d bp:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch_d bp:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bra.cgs b/sim/testsuite/sim/fr30/bra.cgs
new file mode 100644
index 0000000..3732f74
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bra.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bra $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bra
+bra:
+ ; Test bra $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch bra
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch bra
+
+ ; Test bra:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch_d bra:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch_d bra:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ take_branch_d bra:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ take_branch_d bra:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch_d bra:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch_d bra:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ take_branch_d bra:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ take_branch_d bra:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch_d bra:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch_d bra:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ take_branch_d bra:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ take_branch_d bra:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch_d bra:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch_d bra:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ take_branch_d bra:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ take_branch_d bra:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/bv.cgs b/sim/testsuite/sim/fr30/bv.cgs
new file mode 100644
index 0000000..68cb9acf
--- /dev/null
+++ b/sim/testsuite/sim/fr30/bv.cgs
@@ -0,0 +1,109 @@
+# fr30 testcase for bv $label9
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global bv
+bv:
+ ; Test bv $label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch bv
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch bv
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch bv
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch bv
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch bv
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch bv
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch bv
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch bv
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch bv
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch bv
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch bv
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch bv
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch bv
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch bv
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch bv
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch bv
+
+ ; Test bv:d label9
+ set_cc 0x0f ; condition codes are irrelevent
+ take_branch_d bv:d 0xf
+
+ set_cc 0x0e ; condition codes are irrelevent
+ take_branch_d bv:d 0xe
+
+ set_cc 0x0d ; condition codes are irrelevent
+ no_branch_d bv:d 0xd
+
+ set_cc 0x0c ; condition codes are irrelevent
+ no_branch_d bv:d 0xc
+
+ set_cc 0x0b ; condition codes are irrelevent
+ take_branch_d bv:d 0xb
+
+ set_cc 0x0a ; condition codes are irrelevent
+ take_branch_d bv:d 0xa
+
+ set_cc 0x09 ; condition codes are irrelevent
+ no_branch_d bv:d 0x9
+
+ set_cc 0x08 ; condition codes are irrelevent
+ no_branch_d bv:d 0x8
+
+ set_cc 0x07 ; condition codes are irrelevent
+ take_branch_d bv:d 0x7
+
+ set_cc 0x06 ; condition codes are irrelevent
+ take_branch_d bv:d 0x6
+
+ set_cc 0x05 ; condition codes are irrelevent
+ no_branch_d bv:d 0x5
+
+ set_cc 0x04 ; condition codes are irrelevent
+ no_branch_d bv:d 0x4
+
+ set_cc 0x03 ; condition codes are irrelevent
+ take_branch_d bv:d 0x3
+
+ set_cc 0x02 ; condition codes are irrelevent
+ take_branch_d bv:d 0x2
+
+ set_cc 0x01 ; condition codes are irrelevent
+ no_branch_d bv:d 0x1
+
+ set_cc 0x00 ; condition codes are irrelevent
+ no_branch_d bv:d 0x0
+
+ pass
diff --git a/sim/testsuite/sim/fr30/inte.cgs b/sim/testsuite/sim/fr30/inte.cgs
new file mode 100644
index 0000000..a15bfd9
--- /dev/null
+++ b/sim/testsuite/sim/fr30/inte.cgs
@@ -0,0 +1,36 @@
+# fr30 testcase for inte
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global inte
+inte:
+ ; Test inte which is essentially int #9
+ mvr_h_gr tbr,r7
+ inci_h_gr 0x3d8,r7
+ mvi_h_mem pass,r7
+ mvi_h_gr doint,r9
+ inci_h_gr 2,r9
+ mvr_h_gr ssp,r10
+ set_cc 0x0f ; Condition codes should not change
+ set_s_user ; Set opposite of expected
+ set_i 1 ; Should not change
+ mvr_h_gr ps,r8
+doint: inte
+ fail
+
+pass:
+ test_cc 1 1 1 1
+ test_ilm 4
+ test_s_system
+ test_i 1
+ inci_h_gr -4,r10
+ testr_h_mem r8,r10
+ inci_h_gr -4,r10
+ testr_h_mem r9,r10
+ testr_h_dr r10,ssp
+
+ pass
diff --git a/sim/testsuite/sim/fr30/reti.cgs b/sim/testsuite/sim/fr30/reti.cgs
new file mode 100644
index 0000000..76a1af0
--- /dev/null
+++ b/sim/testsuite/sim/fr30/reti.cgs
@@ -0,0 +1,57 @@
+# fr30 testcase for reti
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global reti
+reti:
+ ; Test reti with low reset of ilm allowed
+ mvr_h_gr sp,r8 ; Save stack pointer
+ set_s_system
+ set_i 1
+ set_ilm 15 ; attempt reset of low range
+ set_cc 0x0f ; Condition codes should not change
+ save_ps
+ inci_h_gr -4,sp
+ mvi_h_mem ret1,sp
+ set_i 0 ; Set opposite of expected
+ set_ilm 0 ; attempt reset of low range
+ set_cc 0x00 ; Set opposite of expected
+
+ reti
+ fail
+
+ret1:
+ test_cc 1 1 1 1
+ test_s_system
+ test_i 1
+ test_ilm 15
+ testr_h_gr r8,sp
+
+ ; Test reti with low reset of ilm not allowed
+ mvr_h_gr sp,r8 ; Save stack pointer
+ set_s_system
+ set_i 0
+ set_ilm 15 ; attempt reset of low range
+ set_cc 0x0f ; Condition codes should not change
+ save_ps
+ inci_h_gr -4,sp
+ mvi_h_mem ret2,sp
+ set_i 0 ; Set opposite of expected
+ set_ilm 16 ; disallow reset of low range
+ set_cc 0x00 ; Set opposite of expected
+
+ reti
+ fail
+
+ret2:
+ test_cc 1 1 1 1
+ test_s_system
+ test_i 0
+ test_ilm 31
+ testr_h_gr r8,sp
+
+ pass